NXP Semiconductors MPC5644A, Reference Manual, Page: 1310 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1310 Freescale Semiconductor
Figure 30-42. DSPI modified transfer format (MTFE = 1, CPHA = 0, f
sck
= f
sys
/3)
30.9.6.4 Modified SPI/DSI transfer format (MTFE = 1, CPHA = 1)
Figure 30-43 – Figure 30-45 show the Modified Transfer Format for CPHA = 1. Only the condition, where
CPOL = 0 is shown. At the start of a transfer the DSPI asserts the PCS signal to the slave device. After the
PCS to SCK delay has elapsed the master and the slave put data on their SOUT pins at the first edge of
SCK. The slave samples the master SOUT signal on the even numbered edges of SCK. The master samples
the slave SOUT signal on the odd numbered SCK edges starting with the third SCK edge. The slave
samples the last bit on the last edge of the SCK. The master samples the last slave SOUT bit one half SCK
cycle after the last edge of SCK. No clock edge will be visible on the master SCK pin during the sampling
of the last bit.
The SCK to PCS delay must be greater or equal to half of the SCK period.
Figure 30-43. DSPI modified transfer format (MTFE = 1, CPHA = 1, f
sck
= f
sys
/2)
D0 D1 D2 Dn
D0 D1 D2 Dn
Slave samples SOUT
DSPI samples SIN
Tcsc
Tvd_sl
Tasc
Thd_sl Tsu_sl
Thd_ms
Tsu_ms
sys clk
PCS
SIN
SCK
SOUT
D0 D1 D2 Dn
D0 D1 D2 Dn
Slave samples SOUT
DSPI samples SIN
Tcsc
Tvd_sl
Tasc
Thd_sl
Tsu_sl
Thd_ms
Tsu_ms
sys clk
PCS
SIN
SCK
SOUT
1
2
3
4
5
6
7
8
2n+1
2n+2