NXP Semiconductors MPC5644A, Reference Manual, Page: 1269 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1269
0100 32 1100 8192
0101 64 1101 16384
0110 128 1110 32768
0111 256 1111 65536
Table 30-10. DSPI baud rate scaler
BR Baud rate scaler value BR Baud rate scaler value
0000 2 1000 256
0001 4 1001 512
0010 6 1010 1024
0011 8 1011 2048
0100 16 1100 4096
0101 32 1101 8192
0110 64 1110 16384
0111 128 1111 32768
Table 30-11. DSPI_CTAR0 field description in slave mode
Field Descriptions
0–4
FMSZ[0:4]
Frame Size
The number of bits transferred per frame is equal FMSZ field value plus 1. Minimum valid FMSZ field
value is 3.
5
CPOL
Clock Polarity
The CPOL bit selects the inactive state of the Serial Communications Clock (SCK).
0 The inactive state value of SCK is low
1 The inactive state value of SCK is high
6
CPHA
Clock Phase
The CPHA bit selects which edge of SCK causes data to change and which edge causes data to be
captured.
0 Data is captured on the leading edge of SCK and changed on the following edge
1 Data is changed on the leading edge of SCK and captured on the following edge
7
PE
Parity Enable
PE bit enables parity bit transmission and reception for the frame
0 No parity bit included/checked.
1 Parity bit is transmitted instead of last data bit in frame, parity checked for received frame.
Table 30-9. Delay scaler encoding (continued)
Field value Scaler value Field value Scaler value