NXP Semiconductors MPC5644A, Reference Manual, Page: 542 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
542 Freescale Semiconductor
16.6.26 External Clock Control Register (SIU_ECCR)
The SIU_ECCR controls the timing relationship between the system clock and the external clock
CLKOUT. All bits and fields in the SIU_ECCR are read/write and are reset by the global signals
asynchronous reset signal.
Figure 16-211. External Clock Control Register (SIU_ECCR)
S0x984
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ENGDIV
ENGSSE
0 0 0
EB
T
S
0 EBDF
W
Reset
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
= Unimplemented or Reserved
Table 16-216. SIU_ECCR field description
Field Description
0:15 Reserved
16:23
ENGDIV
Engineering Clock Division Factor. The ENGDIV field specifies the frequency ratio between the system
clock and the ENGCLK. The ENGCLK frequency is divided from the system clock frequency according
to the following equation.
Eqn. 16-2
ENGDIV = 0 is reserved and results in the ENGCLK frequency being equal to the System Clock
Frequency.
24
ENGSSE
Engineering clock (ENGCLK) source select.
0 ENGCLK source is system clock.
1 ENGCLK source is crystal oscillator clock.
25:27 Reserved
28
EBTS
External Bus Tap Select. The EBTS bit changes the phase relationship between the system clock and
CLKOUT. Changing the phase relationship so that CLKOUT is advanced in relation to system clock
increases the output hold time of the external bus signals to a non-zero value. It also increases the output
delay times, increases the input hold times to non-zero values, and decreases the input setup times.
Note: The EBTS bit must not be modified while an external bus transaction is in progress.
ENGCLK
SystemCloc
korCrystalOscillator
ENGDIVx2
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