
External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
278
Freescale Semiconductor
14.2.2
Features
NOTE
This list is a superset list of all possible features the EBI supports. Refer to
Section 14.1, Information Specific to This Device
for a particular device due to package limitations.
•
32-Bit Address bus with transfer size indication (only 24-29 available on pins)
•
32-Bit Data bus (16-bit Data Bus Mode also supported)
•
Multiplexed Address on Data pins (single master)
•
Memory controller with support for various memory types:
— synchronous burst SDR flash and SRAM
— asynchronous/legacy flash and SRAM
•
Burst support (wrapped only)
•
Bus monitor
•
Port size configuration per chip select (16 or 32 bits)
•
Configurable wait states
•
Configurable internal or external transfer acknowledge (TA) per chip select
•
Support for Dynamic Calibration with up to 4 chip-selects
•
Four Write/Byte Enable (WE[0:3]/BE[0:3]) signals
•
Slower-speed clock modes
•
Stop and Module Disable Modes for power savings
•
Optional automatic CLKOUT gating to save power and reduce EMI
•
Misaligned access support (for chip-select accesses only)
•
Compatible with MPC5xx external bus (with some limitations)
14.2.3
Modes of operation
The mode of the EBI is determined by the MDIS, EXTM, and AD_MUX bits in the EBI_MCR. See
Section 14.4.1.1, EBI Module Configuration Register (EBI_MCR)
for details. Slower-speed modes,
Debug Mode, Stop Mode, and Factory Test Mode are modes that the MCU may enter, in parallel to the
EBI being configured in one of its block-specific modes.
14.2.3.1
Single master mode
In Single Master Mode, the EBI responds to internal requests matching one of its regions, but ignores all
externally-initiated bus requests. The MCU is the only master allowed to initiate transactions on the
external bus in this mode; therefore, it acts as a parked master and does not have to arbitrate for the bus
before starting each cycle. Single Master Mode is entered when EXTM=0 and MDIS=0 in the EBI_MCR.
Summary of Contents for MPC5644A
Page 2: ...MPC5644A Microcontroller Reference Manual Rev 6 2 Freescale Semiconductor...
Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...
Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
Page 1440: ...FlexCAN Module MPC5644A Microcontroller Reference Manual Rev 6 1440 Freescale Semiconductor...