NXP Semiconductors MPC5644A, Reference Manual, Page: 1461 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1461
33.5.2.7 Message Buffer Data Size Register (FR_MBDSR)
This register defines the size of the message buffer data section for the two message buffer segments in a
number of two-byte entities.
The CC provides two independent segments for the individual message buffers. All individual message
buffers within one segment have to have the same size for the message buffer data section. This size can
be different for the two message buffer segments.
2 0x2 cycle start — pulse 0 MT start
3 0x3 minislot start — pulse 0 MT start
4 0x4 slot start A
pulse 0 MT start
5 0x5 B
6 0x6 receive data after glitch filtering A
value +4
FR_A_RX
7 0x7 B FR_B_RX
8 0x8 channel idle indicator A
level +5
FR_A_RX
9 0x9 B FR_B_RX
10 0xA syntax error detected A
pulse +4
FR_A_RX
11 0xB B FR_B_RX
12 0xC content error detected A
level +4
FR_A_RX
13 0xD B FR_B_RX
14 0xE receive FIFO almost-full interrupt signals
A
value n.a.
RX FIFO A
Almost Full
Interrupt
15 0xF
B
RX FIFO B
Almost Full
Interrupt
1
Given in PE clock cycles
Base + 0x000C Write: POC:config
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
MBSEG2DS
0
MBSEG1DS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-7. Message Buffer Data Size Register (FR_MBDSR)
Table 33-12. Strobe signal mapping
SEL
Description Channel Type Offset
1
Reference
dec hex