NXP Semiconductors MPC5644A, Reference Manual, Page: 659 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 659
22.4.3.5 eMIOS200 Channel Status Register (EMIOS_CSR[n])
101001b
2
Reserved
1
10101bb
2
Modulus Counter Buffered (Up/Down counter)
10110b0 Output Pulse Width and Frequency Modulation Buffered
10110b1 – 10111b1
2
Reserved
1
11000b0
2
Output Pulse Width Modulation Buffered
1100001 through
1111111
Reserved
1
1
If a reserved value is written to MODE, the results are unpredictable.
2
b = adjust parameters for the mode of operation. Refer to Section 22.5.1.1, Channel modes of operation , for details.
Address: UC[ n ] base a 0x0010 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R OVR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R OVFL 0 0 0 0 0 0 0 0 0 0 0 0 UCIN UCOUT FLAG
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-10. eMIOS200 Channel Status Register (EMIOS_CSR[n])
Table 22-10. EMIOS_CSR[n] field description
Field Description
OVR Overrun
The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set. This bit
can be cleared by clearing the FLAG bit or by software writing a ‘1’.
0 Overrun has not occurred.
1 Overrun has occurred.
OVFL Overflow
The OVFL bit indicates that an overflow has occurred in the internal counter. This bit must be
cleared by software writing a ‘1’.
0 An overflow has not occurred.
1 An overflow has occurred.
UCIN Unified Channel Input Pin
The UCIN bit reflects the input pin state after being filtered and synchronized.
Table 22-9. MODE values (continued)
MODE[0:6] Mode of operation