NXP Semiconductors MPC5644A, Reference Manual, Page: 1420 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
1420 Freescale Semiconductor
32.4.5.13 Rx Individual Mask Registers (RXIMR0
–
RXIMR63)
These registers are used as acceptance masks for ID filtering in Rx message buffers and the FIFO. If the
FIFO is not enabled, one mask register is provided for each available Message Buffer, providing ID
masking capability on a per Message Buffer basis. When the FIFO is enabled (MCR[FEN] is set), the first
eight Mask Registers apply to the eight elements of the FIFO filter table (on a one-to-one correspondence),
while the rest of the registers apply to the regular message buffers, starting from MB8.
The Individual Rx Mask Registers are implemented in RAM, so they are not affected by reset and must be
explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the
module is in Freeze Mode. Out of Freeze Mode, write accesses are blocked and read accesses will return
“all zeros”. Furthermore, if MCR[MBFEN] is negated, any read or write operation to these registers results
in access error.
Table 32-16. IFRL Register field descriptions
Field Description
BUF31I–
BUF8I
Buffer MB
i
Interrupt
Each bit flags the respective FlexCAN Message Buffer (MB8 to MB31) interrupt.
1: The corresponding message buffer has successfully completed transmission or reception
0: No such occurrence
BUF7I Buffer MB7 Interrupt or “FIFO Overflow”
If the FIFO is not enabled, this bit flags the interrupt for MB7. If the FIFO is enabled, this flag
indicates an overflow condition in the FIFO (frame lost because FIFO is full).
1: MB7 completed transmission/reception or FIFO overflow
0: No such occurrence
BUF6I Buffer MB6 Interrupt or “FIFO Warning”
If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag
indicates that 5 out of 6 buffers of the FIFO are already occupied (FIFO almost full).
1: MB6 completed transmission/reception or FIFO almost full
0: No such occurrence
BUF5I Buffer MB5 Interrupt or “Frames available in FIFO”
If the FIFO is not enabled, this bit flags the interrupt for MB5. If the FIFO is enabled, this flag
indicates that at least one frame is available to be read from the FIFO.
1: MB5 completed transmission/reception or frames available in the FIFO
0: No such occurrence
BUF4I–
BUF0I
Buffer MB
i
Interrupt or “reserved”
If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled,
these flags are not used and must be considered as reserved locations.
1: Corresponding message buffer completed transmission/reception
0: No such occurrence