NXP Semiconductors MPC5644A, Reference Manual, Page: 617 / 1735

Software Watchdog Timer (SWT)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 617
Figure 20-3. SWT Time-Out Register (SWT_TO)
20.3.2.4 SWT Window Register (SWT_WN)
The SWT Window (SWT_WN) register contains the 32-bit window start value. This register is cleared on
reset. This register is read-only if either the SWT_MCR[HLK] or SWT_MCR[SLK] bits are set.
Figure 20-4. SWT Window Register (SWT_WN)
20.3.2.5 SWT Service Register (SWT_SR)
The SWT Time-Out (SWT_SR) service register is the target for service operation writes used to reset the
watchdog timer.
Offset 0x008 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R WTO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0
Table 20-4. SWT_TO Register field description
Field Description
WTO Watchdog time-out period in clock cycles
An internal 32-bit down counter is loaded with this value or 0x100 which ever is greater when the service
sequence is written or when the SWT is enabled.
Offset 0x00C Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R WST
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 20-5. SWT_WN Register field description
Field Description
WST Window start value
When window mode is enabled, the service sequence can only be written when the internal down counter
is less than this value.