Avaya Definity SI, Maintenance Manual, Page: 2517 / 2968

TDM-CLK (TDM Bus Clock)
Issue 4 May 2002 10-1731 555-233-123
2000 ABORT Response to the test request was not received within the
allowable time period.
2100 ABORT System resources required to run this test are not available.
1. Retry the command at 1-minute intervals a maximum of 5
times.
Any FAIL The error code represents the number of timing slips detected
on the incoming synchronization source since the last slip
inquiry was sent to the Tone-Clock circuit pack. The incoming
synchronization signal can be from one of four sources:
1. A Stratum 3 Clock, if that option is administered and the
circuit pack tested was the active Tone-Clock in the PPN.
2. A DS1 Interface circuit pack, if DS1 Synchronization is
administered, and associated with the circuit pack tested.
3. The local oscillator on the master Tone-Clock circuit pack,
if it is providing the system clocking signals.
4. An EXP-INTF circuit pack, if the port network on which the
test was executed does not contain the current system
synchronization reference.
The error code is a variable amount ranging from 1 to 255.
1. Small numbers of slips should not result in service
degradation. If the error code is small (1 or 2), rerun the
test. If the error only occurs infrequently, it may be
ignored.
2. Otherwise, refer to the “Approach to Troubleshooting”
section in the Synchronization (SYNC) Maintenance
section of this manual.
PASS The Tone-Clock circuit pack does not detect any timing slips.
This indicates that the incoming synchronization timing source
is valid or that the system synchronization reference is a
Tone-Clock circuit pack. The status synchronization
command should be used to verify that the desired
synchronization reference is providing timing for the system.
Table 10-637. TEST #149 TDM Bus Clock Slip Inquiry Test — Continued
Error
Code Test
Result Description/Recommendation
Continued on next page