Avaya Definity SI, Maintenance Manual, Page: 2214 / 2968

Maintenance Object Repair Procedures
555-233-123 10-1428 Issue 4 May 2002
Processor Bus Time-out Exception Test (#82)
This test is a nondestructive test. The test is used to verify that the RISC
Processor can intentionally cause a BUS TIMEOUT EXCEPTION (BTE) and then
verifies if it vectors to the correct interrupt routine. This is basically a test of the
internal operation of the RISC Processor chip and the bus time-out circuitry.
Table 10-539. Test #82 Processor Bus Time-out Exception Test
Error
Code Test
Result Description/Recommendation
100 ABORT The test did not complete within the allowable time period.
1. Retry the command.
1029
2014
2015
2016
2017
2018
2020
2022
2024
2025
2051 ABORT Refer to STBY-SPE for a description of these error codes.
2500 ABORT Internal system error
1. Retry the command.
FAIL The interrupt was not detected or acted upon.
1. Repeat the command at 1-minute intervals a maximum of 5
times.
2. If the test continues to fail, the Processor circuit pack should
be replaced. The replacement must have enough memory
for this system.
NOTE:
If you replace the Processor circuit pack, you need
to obtain a new license file.
3. If replacement of the Processor circuit pack still results in
test failure, the following circuit packs should be replaced,
one at a time in the order provided: TN765 Processor
Interface, TN777B Network Control, TN778 Packet Control,
and TN772 Duplication Interface circuit packs. The test
should then be repeated.
PASS The interrupt was correctly detected. The RISC Processor is
functioning correctly.
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