Avaya Definity SI, Maintenance Manual, Page: 2514 / 2968

Maintenance Object Repair Procedures
555-233-123 10-1728 Issue 4 May 2002
d. This test only runs on the Standby Tone-Clock circuit pack in a Port
Network with more than one Tone-Clock circuit pack (High or Critical
Reliability Option). The circuit pack must be a TN780 code with firmware
revision 2 or above, or be a TN2182.
e. Test #149 is not run on the TN2182.
TDM Bus Clock Circuit Status Inquiry Test (#148)
The TDM Bus Clock circuitry is checked for sanity. Any problems that are found
are reported via error codes
Table 10-636. TEST #148 TDM Bus Clock Circuit Status Inquiry Test
Error
Code Test
Result Description/Recommendation
None
1001 ABORT The system could not allocate the necessary resources for the
test.
1. Wait 1 minute, and retry the test.
2000 ABORT Response to the test request was not received within the
allowable time period.
2100 ABORT System resources required to run this test are not available.
1. Retry the command at 1-minute intervals a maximum of 5
times.
1 FAIL This error means the Tone-Clock circuit pack framing
verification firmware reports an error in the clock
synchronization signal coming into this Port Network.
1. If the Tone-Clock circuit pack reporting the problem is a
master clock, then the system synchronization reference
is providing a bad timing source. Refer to SYNC
(Synchronization) or STRAT-3 (Stratum 3 Clock)
Maintenance documentation to change the system
synchronization reference.
2. If the Tone-Clock circuit pack is a slave clock, then the EI
to which it is listening is providing a bad timing source.
Follow the diagnostic procedures specified for TDM-CLK
Error Code 2305.
3. If no problem can be found with the incoming
synchronization signal, replace the Tone-Clock circuit
pack. See How to Replace the Tone-Clock Circuit Pack in
the TONE-BD section.
2 FAIL This error indicates that Tone-Clock circuit pack has
inaccurately detected loss of signal on the incoming
synchronization timing source.
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