Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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G-24 ADSP-BF535 Blackfin Processor Hardware Reference
Do not confuse the “SDRAM internal banks” which are internal to the
SDRAM and are selected with the bank address, with the “SDRAM
banks,” or “external banks,” that are enabled by the
SMS[3:0]
pins.
SDRAM DIMMs.
Dual In-line Memory Modules, or DIMMs, are an industry-standard
SDRAM packaging option. The DIMM consists of a small, standardized
form factor board, populated with SDRAM devices on one or both sides.
DIMMs are populated with sufficient SDRAM to provide either 32-bit or
64-bit data paths, with some configurations supporting additional data
bits for parity protection.
Many DIMMs also include a serial presence detect port, which provides
access to an on-DIMM serial ROM that includes information describing
the type and characteristics of SDRAMs on the DIMM. This information
can be read to determine the type, size, and timing parameters of installed
DIMMs at boot time. One of the SPI or SPORT peripherals of the
ADSP-BF535 processor can be used to interface to the DIMM serial pres-
ence detect port, if dynamic boot time determination of SDRAM
configuration is required.
Self-Refresh.
When the SDRAM is in Self-Refresh mode, the SDRAM’s internal timer
initiates Auto-Refresh cycles periodically, without external control input.
The SDC must issue a series of commands including the Self-Refresh
command to put the SDRAM into this low power mode, and it must issue
another series of commands to exit Self-Refresh mode. Entering
Self-Refresh mode is programmable in the SDRAM Memory Global Con-
trol register (
EBIU_SDGCTL
) and any access to the SDRAM address space
causes the SDC to exit the SDRAM from Self-Refresh mode. See “Enter-
ing and Exiting Self-Refresh Mode (SRFS)” on page 18-44 .
Serial Peripheral Interface (SPI).
A synchronous serial protocol used to connect integrated circuits.