Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-1
18 EXTERNAL BUS INTERFACE
UNIT
The ADSP-BF535 processor’s External Bus Interface Unit (EBIU) pro-
vides glueless interfaces to external memories. The ADSP-BF535
processor supports synchronous DRAM (SDRAM) and is compliant with
the PC100 and PC133 SDRAM standards. The EBIU also supports asyn-
chronous interfaces such as SRAM, ROM, FIFOs, flash memory, and
ASIC/FPGA designs.
The EBIU is clocked by the system clock (
SCLK
). All synchronous memo-
ries interfaced to the ADSP-BF535 processor operate at the
SCLK
frequency. The ratio between core frequency and
SCLK
frequency is pro-
grammable using a PLL system MMR. For more information, see “Core
Clock/System Clock Ratio Control” on page 8-5.
The external memory space is shown in Figure 18-1 . Four of the memory
regions are dedicated to SDRAM support. SDRAM interface timing and
the size of each SDRAM region are programmable. Each SDRAM bank
can range in size from 16 MBytes to 128 MBytes. The start address of
bank 0 is 0x0000 0000. The start addresses of banks 1, 2, and 3 follow
contiguously from the previous bank. If all four SDRAM banks are not
fully populated with 128 MBytes of SDRAM, the area from the end of
bank 3 to address 0x2000 0000 is reserved.
The next four regions are dedicated to supporting asynchronous memo-
ries. Each asynchronous memory region can be independently
programmed to support different memory device characteristics. Each
region has its own memory-select output pin from the EBIU.