Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 274 / 1022

Data Test Registers
6-48 ADSP-BF535 Blackfin Processor Hardware Reference
When the Data Test Command register (
DTEST_COMMAND
) is written to, the
L1 cache data or tag arrays are accessed and data is transferred through the
Data Test Data registers (
DTEST_DATA[1:0]
). The
DTEST_DATA[1:0]
regis-
ters contain the 64-bit data to be written, or they contain the destination
for the 64-bit data read. The lower 32-bits are stored in the
DTEST_DATA[0]
and the upper 32-bits are stored in the
DTEST_DATA[1]
reg-
ister. When the tag arrays are being accessed, then
DTEST_DATA[0
] is used.

Before accessing the cache entries through the
DTEST
registers,
enable the L1 Data memories by setting the
ENDM
and
DMC[1:0]
bits
and clearing the
ENDCPLB
bit in
DMEM_CONTROL
register.
These figures describe the
DTEST
registers:
• Data Test Command Register in Figure 6-15 on page 6-49
• Data Test Data 1 Register in Figure 6-16 on page 6-50
• Data Test Data 0 Register in Figure 6-17 on page 6-51
Access to these registers is possible only in Supervisor or Emulation mode.
When writing to
DTEST
registers, always write to the
DTEST_DATA
registers
first, then the
DTEST_COMMAND
register. When reading from
DTEST
registers,
reverse the sequence. Always read the
DTEST_COMMAND
register first, then
the
DTEST_DATA
registers.