Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 14-7
USB Device
Front-End Interface Block
The Front-End Interface consists of all blocks in the block diagram except
the UDC. These blocks are:
• Clock Control
• Transaction Decode and Clock Synchronization
• Registers and Control
• Memory Interface
• DMA Master
• PAB Interface
Each is described in the following sections.
Clock Control Block
To reduce power consumption, the UDC module uses gated clocks. The
gated-clock control circuit ensures error-free clocking to the UDC module
in a DFT (design for testability) friendly way.
Transaction Decode and Clock Synchronization
Block
The transaction decode module includes synchronizer elements to connect
the system clock domain logic at the system clock rate to the USB logic at
12 MHz.
It also decodes transactions that occur on the UDC’s application bus for
presentation to the other submodules. This module routes endpoint trans-
actions to and from the Memory Interface module, and control,
configuration, and status functions to and from the Registers and Control
module.