Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Events and Sequencing
4-30 ADSP-BF535 Blackfin Processor Hardware Reference
These registers can be read or written at any time in Supervisor mode. It is
advisable, however, to configure them in the Reset interrupt service rou-
tine before enabling interrupts. To prevent spurious or lost interrupt
activity, these registers should be written to only when all peripheral inter-
rupts are disabled.
Figure 4-10. System Interrupt Assignment Register 1
Figure 4-11. System Interrupt Assignment Register 2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1
SPI0 Interrupt
IVG select
SPI1 Interrupt
IVG select
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1
UART1 RX Interrupt
IVG select
UART1 TX Interrupt
IVG select
Timer 1 Interrupt
IVG select
Timer 0 Interrupt
IVG select
UART0 TX Interrupt
IVG select
UART0 RX Interrupt
IVG select
System Interrupt Assignment Register 1 (SIC_IAR1)
Reset = 0x4433 3322
0xFFC0 0C08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
System Interrupt Assignment Register 2 (SIC_IAR2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0
Memory DMA Interrupt
IVG select
PF Interrupt B
IVG select
Software Watchdog Timer
Interrupt
IVG select
Reset = 0x0006 6554
Timer 2 Interrupt
IVG select
PF Interrupt A
IVG select
0xFFC0 0C0C