Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference B-17
System MMR Assignments
0xFFC0 2832 SPORT0_MCMC1 “SPORTx Multichannel Receive
Select (SPORTx_MRCSx) Registers”
on page 11-27
0xFFC0 2834 SPORT0_MCMC2 “SPORTx Multichannel Configura-
tion (SPORTx_MCMCx) Registers”
on page 11-29
0xFFC0 2A00 SPORT0_CURR_PTR_RX “SPORTx Receive DMA Current
Descriptor Pointer
(SPORTx_CURR_PTR_RX) Regis-
ters” on page 11-31
0xFFC0 2A02 SPORT0_CONFIG_DMA_RX “SPORTx Receive DMA Configura-
tion
(SPORTx_CONFIG_DMA_RX)
Registers” on page 11-31
0xFFC0 2A04 SPORT0_START_ADDR_HI_RX “SPORTx Receive DMA Start
Address High
(SPORTx_START_ADDR_HI_RX)
Registers” on page 11-34
0xFFC0 2A06 SPORT0_START_ADDR_LO_RX “SPORTx Receive DMA Start
Address Low
(SPORTx_START_ADDR_LO_RX)
Registers” on page 11-35
0xFFC0 2A08 SPORT0_COUNT_RX “SPORTx Receive DMA Count
(SPORTx_COUNT_RX) Registers”
on page 11-36
0xFFC0 2A0A SPORT0_NEXT_DESCR_RX “SPORTx Receive DMA Next
Descriptor Pointer
(SPORTx_NEXT_DESCR_RX)
Registers” on page 11-36
0xFFC0 2A0C SPORT0_DESCR_RDY_RX “SPORTx Receive DMA Descriptor
Ready (SPORTx_DESCR_RDY_RX)
Registers” on page 11-37
Table B-10. SPORT0 Controller Registers (Cont’d)
Memory-Mapped
Address Register Name See Section