Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 19-9
System Design
External Memory Design Issues
This section describes design issues related to external memory including
supported SDRAM configurations, examples of SDRAM and SRAM
interfaces, and how to avoid bus contention on the external memory bus.
Example Asynchronous Memory Interfaces
This section shows glueless connections to 32-bit and 16-bit wide SRAM.
Note this interface does not require external assertion of
ARDY
, since the
internal wait state counter is sufficient for deterministic access times of
memories.
Figure 19-3 shows the glueless interface to 32-bit SRAM. Note that this
application requires the 32-bit datapath mode to be enabled for this bank
of memory in the Asynchronous Memory Global Control Register.
Figure 19-4 shows the system interconnect required to support 16-bit
memories. Note this application requires that the 16-bit packing mode be
enabled for this bank of memory. Otherwise, the programming model
must ensure that every other 16-bit memory location is accessed starting
on an even (byte address[1:0]=00) 16-bit address.
Figure 19-3. Interface to 32-bit SRAM
ADSP-BF535
AMS[X]
AOE
AWE
ABE[3:0]
ADDR[N+2:2]
DATA[31:0]
ARE
ARDY
CE
OE
R/W
32-BIT SRAM
UB[1:0], LB[1:0]
A[N:0]
D[31:0]