Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-43
External Bus Interface Unit
The
X16DE
bit is used to select whether the SDRAM interface is 32 bits
wide or 16 bits wide. If
X16DE
is 0,
DATA[31:0]
should be connected to the
SDRAM. If
X16DE
is 1,
DATA[15:0]
should be connected to the SDRAM.
Note that all SDRAM banks must be either all 32 bits wide or all 16 bits
wide.
Setting the SDRAM Clock Enables (SCTLE and SCK1E)
To meet higher clock load requirements for systems with multiple
SDRAM devices, the ADSP-BF535 processor provides two SDRAM clock
control pins,
SCLK[0]
and
SCLK[1]
. These pins eliminate the need for
off-chip clock buffers for most system memory configurations. The
SCTLE
and
SCK1E
bits in the SDRAM Memory Global Control register
(
EBIU_SDGCTL
) provide control for the SDRAM clock control pins.
The
SCTLE
bit disables all of the SDRAM control pins:
SDQM[3:0]
,
SCAS
,
SRAS
,
SWE
,
SCKE
, and the
SCLK[0]
.
SCTLE = 0
Disable all SDRAM control pins (control pins deas-
serted,
SCLK[0]
low)
SCTLE = 1
Enable all SDRAM control pins (
SCLK[0]
toggles)
The
SCK1E
bit disables the
SCLK[1]
pin independently:
SCK1E = 0
Disable
SCLK[1]
(
SCLK[1]
low)
SCK1E = 1
Enable
SCLK[1]
(
SCLK[1]
toggles)
Note the
SCLK[1]
function is also shared with the Asynchronous Memory
Controller (AMC). Even if
SCTLE
and
SCK1E
are disabled,
SCLK[1]
can be
enabled independently by the
CLKOUT
enable in the AMC (
AMCKEN
in the
EBIU_AMGCTL
register).
If the system does not use SDRAM, both
SCTLE
and
SCK1E
should be 0.