Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-61
Memory
CPLB Management
When the Blackfin processor issues a memory operation for which no
valid CPLB descriptor exists in an MMR pair, an exception occurs that
places the processor into Supervisor mode and vectors to the MMU excep-
tion handler (see
“Exceptions” on page 4-38 for more information). The
handler is typically part of the operating system kernel that implements
the CPLB replacement policy.

Before CPLBs are enabled, valid CPLB descriptors must be in place
for both the Page Descriptor Table and the MMU exception han-
dler. The
LOCK
bit of these CPLB descriptors are commonly set so
that they are not inadvertently replaced.
The handler uses the faulting address to index into the Page Descriptor
Table structure to find the correct CPLB descriptor data to load into one
of the on-chip CPLB register pairs. If all on-chip registers contain valid
CPLB entries, the handler selects one of the descriptors to be replaced,
and the new descriptor information is loaded. Before loading new descrip-
tor data into any CPLBs, the corresponding group of sixteen CPLBs must
be disabled by clearing the Enable DCPLB (
ENDCPLB
) bit in the
DMEM_CONTROL
register for data descriptors or the Enable ICPLB (
ENICPLB
)
bit in the
IMEM_CONTROL
register for instruction descriptors.
The CPLB replacement policy and algorithm to be used are the responsi-
bility of the system MMU exception handler. This policy, which is
dictated by the characteristics of the operating system, usually implements
a modified LRU (Least Recently Used) policy, a round-robin scheduling
method, or pseudo-random replacement.
After the new CPLB descriptor is loaded, the exception handler returns,
and the faulting memory operation restarted. It should then find a valid
CPLB descriptor for the requested address, and the operation should
proceed.