Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-51
External Bus Interface Unit
The
EBIU_SDBCTL
register stores the configuration information for each
SDRAM bank interface. The EBIU supports 64 Mbit, 128 Mbit, 256
Mbit, and 512 Mbit SDRAM devices with x4, x8, x16 configurations. See
“SDRAM External Bank Address Decode” on page 18-56 for more infor-
mation on bank starting address decodes.
The SDC determines the internal SDRAM page size from the
X16DE
and
EBxCAW
parameters. Page sizes of 1 KB, 2 KB, 4 KB, and 8 KB are sup-
ported. Table 18-5 shows the page size and breakdown of the internal
address (
IA[31:0]
, as seen from the core, DMA, or PCI) into the row,
bank, column, and byte address. The column address and the byte address
together make up the address inside the page.
The bank address can be thought of as part of the row address. The com-
binations of external bank width (
X16DE
), external bank size (
EBxSZ
) and
column address width (
EBxCAW
) which are not supported are also indicated
in this table. Programming the SDC with non-supported values produces
unpredictable results.
The
EBxE
bits in the
EBIU_SDBCTL
register are used to enable or disable a
bank. If a bank is disabled, any access to the address space of that disabled
bank generates an internal bus error, and the access does not occur exter-
nally.
For more information, see “Error Detection” on page 18-8. Note
that the size (
EBxSZ
) of all banks, regardless of whether they are enabled or
disabled, is used in determining the bank starting addresses.
Table 18-5. Internal Address Mapping
Bank
Width
Bits Bank
Size
Mbyte Col
Addr
Width
(CAW Page
Size
kbyte Row
Address Bank
Address Page SDRAM Config
Column
Address Byte
Address Size
Mbit Width
Bits Num
Chips
32 128 11 8 IA[26:15] IA[14:13] IA[12:2] IA[1:0] 128 4 8
32 128 10 4 IA[26:14] IA[13:12] IA[11:2] IA[1:0] 256 8 4
512 16 2