Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Branches and Sequencing
4-14 ADSP-BF535 Blackfin Processor Hardware Reference
whether the value of the
CC
flag is true or false (1 or 0). In some cases,
using this instruction instead of a branch eliminates the cycles lost because
of the branch.
Example code:
IF CC R0 = P0 ;
Branch Prediction
The Sequencer supports static branch prediction to accelerate execution of
conditional branches. These branches are executed based on the state of
the
CC
bit.
The branch target address calculation takes place in the AC stage of the
instruction pipeline. In the EX3 stage, the Sequencer compares the actual
CC
bit value to the predicted value. If the value was mis-predicted, the
branch is corrected, and the correct address is available for the WB stage
of the pipeline.
The branch latency for conditional branches is as follows:
• If prediction was “not to take branch,” and branch was actually not
taken: 0
CCLK
cycles.
• If prediction was “not to take branch,” and branch was actually
taken: 6
CCLK
cycles.
• If prediction was “to take branch,” and branch was actually taken:
3
CCLK
cycles.
• If prediction was “to take branch,” and branch was actually not
taken: 6
CCLK
cycles.
For all unconditional branches, the branch target address computed in the
AC stage of the pipeline is sent to the Instruction Fetch address bus at the
beginning of the EX1 stage. All unconditional branches have a latency of 3
CCLK
cycles.