Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 894 / 1022

SPORT1 Controller Registers
B-22 ADSP-BF535 Blackfin Processor Hardware Reference
0xFFC0 2E04 SPORT1_START_ADDR_HI_RX “SPORTx Receive DMA Start
Address High
(SPORTx_START_ADDR_HI_RX)
Registers” on page 11-34
0xFFC0 2E06 SPORT1_START_ADDR_LO_RX “SPORTx Receive DMA Start
Address Low
(SPORTx_START_ADDR_LO_RX)
Registers” on page 11-35
0xFFC0 2E08 SPORT1_COUNT_RX “SPORTx Receive DMA Count
(SPORTx_COUNT_RX) Registers”
on page 11-36
0xFFC0 2E0A SPORT1_NEXT_DESCR_RX “SPORTx Receive DMA Next
Descriptor Pointer
(SPORTx_NEXT_DESCR_RX)
Registers” on page 11-36
0xFFC0 2E0C SPORT1_DESCR_RDY_RX “SPORTx Receive DMA Descriptor
Ready (SPORTx_DESCR_RDY_RX)
Registers” on page 11-37
0xFFC0 2E0E SPORT1_IRQSTAT_RX “SPORTx Receive DMA IRQ Status
(SPORTx_IRQSTAT_RX) Registers”
on page 11-38
0xFFC0 2F00 SPORT1_CURR_PTR_TX “SPORTx Transmit DMA Current
Descriptor Pointer
(SPORTx_CURR_PTR_TX) Regis-
ters” on page 11-39
0xFFC0 2F02 SPORT1_CONFIG_DMA_TX “SPORTx Transmit DMA Configu-
ration
(SPORTx_CONFIG_DMA_TX)
Registers” on page 11-40
0xFFC0 2F04 SPORT1_START_ADDR_HI_TX “SPORTx Transmit DMA Start
Address High
(SPORTx_START_ADDR_HI_TX)
Registers” on page 11-43
Table B-11. SPORT1 Controller Registers (Cont’d)
Memory-Mapped
Address Register Name See Section