Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 4-35
Program Sequencer
Event Vector Table
The Event Vector Table (EVT) is a hardware table with sixteen entries
that are each 32 bits wide. The EVT contains an entry for each possible
core event. Entries are accessed as MMRs, and each entry can be pro-
grammed at reset with the corresponding vector address for the interrupt
service routine. When an event occurs, instruction fetch starts at the
address location in the EVT entry for that event.
The ADSP-BF535 processor architecture allows unique addresses to be
programmed into each of the interrupt vectors; that is, interrupt vectors
are not determined by a fixed offset from an interrupt vector table base
address. This approach minimizes latency by not requiring a long jump
from the vector table to the actual ISR code.
Table 4-9 lists events by priority. Each event has a corresponding bit in
the event state registers
ILAT
,
IMASK
, and
IPEND
.
Table 4-9. Core Event Vector Table
Event Number Event Class Name MMR Location Notes
EVT0 Emulation EMU 0xFFE0 2000 Highest priority. Vec-
tor address is provided
by JTAG.
EVT1 Reset RST 0xFFE0 2004 Read-only.
EVT2 NMI NMI 0xFFE0 2008
EVT3 Exception EVX 0xFFE0 200C
EVT4 Reserved Reserved 0xFFE0 2010 Reserved vector.
EVT5 Hardware Error IVHW 0xFFE0 2014
EVT6 Core Timer IVTMR 0xFFE0 2018
EVT7 Interrupt 7 IVG7 0xFFE0 201C
EVT8 Interrupt 8 IVG8 0xFFE0 2020
EVT9 Interrupt 9 IVG9 0xFFE0 2024