Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Memory Architecture
6-34 ADSP-BF535 Blackfin Processor Hardware Reference
Listing 6-2. Invalidating Data Cache
I0.L = (DTEST_COMMAND & 0xFFFF);
I0.H = (DTEST_COMMAND >> 16);
I1.L = (DTEST_DATA0 & 0xFFFF);
I1.H = (DTEST_DATA0 >> 16);
R0.L = 0;
R0.H = 0;
[I1] = R0;
/* Repeat for data cache */
/* Explanation: The invalidation routine is as follows: */
/* Cache construction: */
/* D-CACHE: */
/* 2 data banks, */
/* each data bank has 4 sub-banks, */
/* each sub-bank has 2 ways, */
/* each way has 64 lines, */
/* each line (or set) has 4 double words. */
/* Routine: */
/* - Take way 0, and way1 */
/* - Inner loop: */
/* Invalidate all sets (cache lines) in sub-bank for way 0
and way1 */
/* Instruction Cache has 64 sets (cache lines), hence loop
count is 64 */
/* - Outer loop: */
/* Increment sub-banks */
/* repeat inner loop */
/* do it 4 times because of 4 sub-banks. */
/* - Repeat again for superbank B */