Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-80 ADSP-BF535 Blackfin Processor Hardware Reference
Self-Refresh mode. If a transfer occurs to SDRAM address space when the
SCTLE
bit is cleared, an internal bus error is generated, and the access does
not occur externally, leaving the SDRAM in Self-Refresh mode. For more
information, see “Error Detection” on page 18-8.
No Operation/Command Inhibit Commands
The No Operation (NOP) command to the SDRAM has no effect on
operations currently in progress. The Command Inhibit command is the
same as a NOP command; however, the SDRAM is not chip-selected.
When the SDC is actively accessing the SDRAM but needs to insert addi-
tional commands with no effect, the NOP command is given. When the
SDC is not accessing any SDRAM external banks, the Command Inhibit
command is given.
SDRAM Timing Specifications
To support key timing requirements and power-up sequences for different
SDRAM vendors, the SDC provides programmability for t
RAS
, t
RP
, t
RCD
,
t
WR
and the power-up sequence mode. ( For more information, see
“SDRAM Memory Global Control Register (EBIU_SDGCTL)” on
page 18-37.
) CAS latency should be programmed in the
EBIU_SDGCTL
reg-
ister based on the frequency of operation. (Refer to the SDRAM vendor’s
data sheet for more information.)
For other parameters, the SDC assumes:
• Bank Cycle Time: t
RC
= t
RAS
+ t
RP
• Refresh Cycle Time: t
RFC
= t
RAS
+ t
RP
• Exit Self-Refresh Time: t
XSR
= t
RAS
+ t
RP
• Load Mode Register to Activate Time: t
MRD
= 2
SCLK
cycles