Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-67
External Bus Interface Unit
Data Mask (SDQM[3:0]) Encodings
During write transfers to SDRAM, the
SDQM[3:0]
pins are used to mask
writes to bytes that are not accessed. Table 18-16 shows the
SDQM[3:0]
encodings for 32-bit wide SDRAM banks based on the internal transfer
address bits
IA[1:0]
and the transfer size.
Table 18-15. 16-Bit SDRAM Bank, 11 Column Address Pins
ADSP-BF535
Processor Address Pin Internal Address
for RAS Internal Address
for CAS SDRAM Address
Pin
ADDR[13] IA[26] A[12]
ADDR[12] IA[25]
IA[11]
A[11]
SA[10] IA[24] A[10]
ADDR[10] IA[23]
IA[10]
A[9]
ADDR[9] IA[22]
IA[9]
A[8]
ADDR[8] IA[21] IA[8] A[7]
ADDR[7] IA[20] IA[7] A[6]
ADDR[6] IA[19] IA[6] A[5]
ADDR[5] IA[18] IA[5] A[4]
ADDR[4] IA[17] IA[4] A[3]
ADDR[3] IA[16] IA[3] A[2]
ADDR[2] IA[15] IA[2] A[1]
ADDR[1] IA[14] IA[1] A[0]
ADDR[19] IA[13] IA[13] BA[1]
ADDR[18] IA[12]
I
A[12] BA[0]
Possible configurations:
2 chips: 512 Mb - 16 M

8

4 banks (128 MB)
4 chips: 256 Mb - 16 M

4

4 banks (128 MB)
4 chips: 128 Mb - 8 M

4

4 banks (64 MB)