Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Configuration Space Control and Status Registers
13-38 ADSP-BF535 Blackfin Processor Hardware Reference
PCI Configuration Memory Base Address Register
(PCI_CFG_MBAR)
The
PCI_CFG_MBAR
register, shown in Figure 13-21 , holds the memory
base address from the PCI configuration registers. The lower 4 bits are
hardcoded, and tell the configuration software to use this register for a
prefetchable memory base address and to place it in the lower 4 Gbytes
(32 bits) of address space. The
PCI_DMBARM
register configures the upper
bits to be writable from the PCI side. Configuration software detects the
size requested by looking at the number of writable upper bits and places a
base address in this space. This register is unused in Host mode. For more
information, see the PCI Local Bus Specification Rev. 2.2.
Figure 13-21. PCI Configuration Memory Base Address Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
PCI Configuration Memory Base Address Register (PCI_CFG_MBAR)
Base Address [31:16]
Base Address [15:4]
00 - Lower 4 GB
01 - Below 1 MB
10 - Over 4 GB
11 - Reserved
0 - Memory space
1 - I/O space
Memory Space Indicator
RO
Type[1:0] - RO
0 - Not prefetchable
1 - Prefetchable
Prefetchable - RO
RO
Reset = 0x0000 0008
0xEEFF FF30