Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-48 ADSP-BF535 Blackfin Processor Hardware Reference
The t
RAS
parameter allows the ADSP-BF535 processor to adapt to the
timing requirements of the system’s SDRAM devices.
The
TRAS
bits in the SDRAM Memory Global Control register
(
EBIU_SDGCTL
) select the t
RAS
value. Any value between 1 and 15
SCLK
cycles can be selected. For example:
TRAS = 0000
No effect
TRAS = 0001
1 clock cycle
TRAS = 0010
2 clock cycles
TRAS = 1111
15 clock cycles
For specific information on setting this value, consult the SDRAM device
documentation.
Selecting the Precharge Delay (TRP)
The t
RP
value (Precharge delay) defines the required delay, in number of
SCLK
cycles, between the time the SDC issues a Precharge command and
the time it issues a Bank Activate command. The t
RP
also specifies the
time required between Precharge and Auto-Refresh, and between Pre-
charge and Self-Refresh. The t
RP
and t
RAS
values define the t
RFC
, t
RC
, and
t
XSR
values.
This parameter enables the application to accommodate the SDRAM’s
timing requirements.
The
TRP
bits in the SDRAM Memory Global Control register
(
EBIU_SDGCTL
) select the t
RP
value. Any value between 1 and 7
SCLK
cycles
may be selected. For example:
TRP = 000
No effect
TRP = 001
1 clock cycle