Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference G-3
burst type.
The burst type determines the address order in which the SDRAM deliv-
ers burst data after detecting a read command or stores burst data after
detecting a write command. The burst type is programmed in the
SDRAM during the SDRAM power-up sequence.
Since the SDRAM burst length is always programmed to be 1, the burst
type does not matter. However, the SDC always sets the burst type to
sequential-accesses-only during the SDRAM power-up sequence.
cache block.
The smallest unit of memory that is transferred to/from the next level of
memory from/to a cache as a result of a cache miss.
cache hit.
A memory access that is satisfied by a valid, present entry in the cache.
cache line.
Same as block. In this document, cache line is used for cache block .
cache miss.
A memory access that does not match any valid entry in the cache.
Cacheability Protection Lookaside Buffer (CPLB).
Storage area that describes the access characteristics of the core memory
map.
CAM (Content Addressable Memory).
Also called Associative Memory. A memory device that includes compari-
son logic with each bit of storage. A datum is broadcast to all words in
memory; the datum is compared with the stored values; and values that
match are flagged.