Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Arithmetic Logic Unit (ALU)
2-28 ADSP-BF535 Blackfin Processor Hardware Reference
adds the 32-bit contents of
R2
to the 32-bit contents of
R1
and deposits the
result in
R3
.
The instruction also subtracts the 32-bit contents of
R2
from that of
R1
and deposits the result in
R4
with no saturation.
A specialized form of this instruction uses the ALU 40-bit result registers
as input operands, creating the sum and differences of the
A0
and
A1
registers.
For example:
R3 = A0 +A1, R4 = A0-A1 (S) ;
transfers to the result registers two 32-bit, saturated, sum and difference
values of the ALU registers.
ALU Instruction Summary
For information about assembly language syntax and the effect of ALU
instructions on the status flags, see Appendix A, “ADSP-BF535 Consider-
ations”, in the
Blackfin Processor Programming Reference .
ALU Data Flow Details
Figure 2-10 shows a more detailed diagram of the Arithmetic Units and
Data Register File, which appears in Figure 2-1 on page 2-2 .
ALU0 is described here for convenience. ALU1 is very similar—a subset of
ALU0.
Each ALU performs 40-bit addition for the accumulation of the multiplier
results, as well as 32-bit and dual 16-bit operations. Each ALU has two
32-bit input ports that can be considered a pair of 16-bit operands or a
single 32-bit operand. For single 16-bit operations, any of the four
possible 16-bit operands may be used with any of the other 16-bit oper-
ands presented at the input to the ALU.