Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 119 / 1022

ADSP-BF535 Blackfin Processor Hardware Reference 2-39
Computational Units
One of the operands must be selected from the low half or the high half of
one 32-bit word. The other operand must be selected from the low half or
the high half of the other 32-bit word. Thus, each MAC is presented with
four possible input operand combinations. The two 32-bit words can con-
tain the same register information giving the options for squaring and
multiplying the high half and low half of the same register.
Figure 2-14
show these possible combinations.
The 32-bit product is passed to a 40-bit adder/subtracter, which may add
or subtract the new product from the contents of the accumulator result
register or pass the new product directly to the Data Register File results
register. For results, the
A0
and
A1
registers are 40 bits wide. Each of these
registers consists of smaller 32-bit and 8-bit registers:
A0.W
,
A1.W
,
A0.X,
and
A1.X
.
Some example instructions follow:
A0 = R3.L * R4.H (S) ;
The
MAC0
multiplier/accumulator performs a multiply and puts the result
in the accumulator register.
A1 += R3.H * R4.H (S) ;
The
MAC1
multiplier/accumulator performs a multiply and accumulates
the result with the previous results in the
A1
accumulator.