Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 8-17
Dynamic Power Management
Table 8-5 summarizes the allowed operating mode transitions.

Attempting to cause mode transitions other than those shown in
Table 8-5 causes unpredictable behavior.
Programming Operating Mode Transitions
The operating mode of the ADSP-BF535 processor is defined by the state
of the
PLL_OFF
,
BYPASS
,
STOPCK
and
PDWN
bits of the PLL Control register
(
PLL_CTL
). Simply modifying the bits of the
PLL_CTL
register does not
change the operating mode or the behavior of the PLL. Changes to the
PLL_CTL
register are realized only after executing a specific code sequence,
which is shown below. This code sequence first brings the ADSP-BF535
processor to a known, idled state. Once in this idled state, the PLL recog-
nizes and implements the changes made to the
PLL_CTL
register. After the
changes take effect, the ADSP-BF535 processor operates with the new set-
tings, including the new operating mode, if one is programmed.
PLL Programming Sequence
Assuming that the PLL Control register (
PLL_CTL
) has been modified with
the new values, the instruction sequence shown in Listing 8-1 puts those
changes into effect.
Table 8-5. Allowed Operating Mode Transitions
New Modes
Current Mode
Full On Active Sleep Deep Sleep
Full On – Allowed Allowed –
Active Allowed – Allowed Allowed
Sleep Allowed Allowed – –
Deep Sleep Allowed Allowed – –