Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-82 ADSP-BF535 Blackfin Processor Hardware Reference
Table 18-19. Throughput for Accesses to 32-Bit Wide SDRAM
Accesses Read/Write
Page Hit/Miss
1 Throughput
L1 Cache Line Fill
(

5 word Read Buffer Hit)
Read Page Hit 8 words/8 cycles
L1 Cache Line Fill
(N word Read Buffer Hit, where
N < 5) Read Page Hit N word hit: 8
words/(13-N) cycles
L1 Cache Line Fill
(Read Buffer Miss) Read Page Hit 8 words/13 cycles
L1 Cache Copyback Write Page Hit 8 words/16 cycles
DMA Burst Read (4 words) Read Page Hit 4 words/9 cycles
DMA Burst Write (4 words) Write Page Hit 4 words/8 cycles
DMA Burst Read (8 words) Read Page Hit 8 words/13 cycles
DMA Burst Write (8 words) Write Page Hit 8 words/16 cycles
Single Read Read Page Hit 1 word/6 cycles
Single Write Write Page Hit 1 word/2 cycles
L1 Cache Line Fill
(Read Buffer Miss) Read Page Miss 8 words/17 cycles
L1 Cache Copyback Write Page Miss 8 words/20 cycles
DMA Burst Read (4 words) Read Page Miss 4 words/13 cycles
DMA Burst Write (4 words) Write Page Miss 4 words/12 cycles
DMA Burst Read (8 words) Read Page Miss 8 words/17 cycles
DMA Burst Write (8 words) Write Page Miss 8 words/20 cycles
Single Read Read Page Miss 1 word/10 cycles
Single Write Write Page Miss 1 word/6 cycles
1 Page Miss Penalty = t
RP
+ t
RCD