Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 238 / 1022

Memory Architecture
6-12 ADSP-BF535 Blackfin Processor Hardware Reference
Level 1 Memory
Figure 6-3 and Figure 6-4 show the Data Memory Control register
(
DMEM_CONTROL
) and Instruction Memory Control register (
IMEM_CONTROL
),
respectively. The bits in these registers can be used to configure L1 Data
Memory and L1 Instruction Memory.
The sections after the figures describe the instruction and data memories
in more detail—including SRAM and cache configurations for each type
of L1 memory.

L1 Instruction Memory can be used only to store instructions, and
L1 Data Memory can be used only to store data.
Data Memory Control Register (DMEM_CONTROL)
The Data Memory Control register (
DMEM_CONTROL
), shown in Figure 6-3 ,
contains control bits for the L1 Data Memory. The reset values of the
ENDM
and
DMC
bits indicate that the L1 Instruction Memory is enabled and
configured as SRAM after reset. The
ENDCPLB
bit is used to enable/disable
the sixteen Cacheability Protection Lookaside Buffers (CPLBs) used for
data (see
“L1 Data Cache” on page 6-40 ).
Instruction Memory Control Register
(IMEM_CONTROL)
The Instruction Memory Control register (
IMEM_CONTROL
), shown in
Figure 6-4 , contains control bits for the L1 Instruction Memory. The
reset values of the
ENIM
and
IMC
bits indicate that the L1 Instruction Mem-
ory is enabled and configured as SRAM after reset. The
ENICPLB
bit is used
to enable/disable the sixteen CPLBs used for instructions (see “L1 Instruc-
tion Cache” on page 6-17 ).