Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-78 ADSP-BF535 Blackfin Processor Hardware Reference
Read/Write Command
A Read/Write command is executed if the next read/write access is in the
present active page. During the Read command, the SDRAM latches the
column address. The delay between Activate and Read commands is deter-
mined by the t
RCD
parameter. Data is available from the SDRAM after
the CAS latency has been met.
In the Write command, the SDRAM latches the column address. The
write data is also valid in the same cycle. The delay between Activate and
Write commands is determined by the t
RCD
parameter.
In cases where the internal bus transfer is an L1 cache line fill burst-read
operation, the SDC attempts to service the line fill with data stored in the
read buffer. For each part of the line fill not available in the read buffer,
the SDC issues a Read command. The SDC then speculatively issues Read
commands if certain conditions are met.
For more information, see “Read
Buffer (Prefetch) Operation” on page 18-72.
The SDC never speculatively issues a write command to the SDRAM.
In the case of a page miss, the SDRAM is precharged and activated before
issuing the Read or Write command. If the internal refresh counter asserts
a refresh request, any new access is delayed until the Auto-Refresh cycle
completes.
The SDC does not use the auto-precharge function of SDRAMs, which is
enabled by asserting
SA10
high during a Read or Write command.
Auto-Refresh Command
The SDRAM internally increments the refresh address counter and causes
a CAS before RAS (
CBR
) refresh to occur internally for that address when
the Auto-Refresh command is given. The SDC generates an Auto-Refresh
command after the SDC refresh counter times out. The
RDIV
value in the
SDRAM Refresh Rate Control register must be set so that all addresses are