Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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PCI Programming Model
13-18 ADSP-BF535 Blackfin Processor Hardware Reference
PCI Programming Model
The PCI interface programming model includes memory-mapped control
and status registers, as well as memory-mapped PCI spaces (configuration,
I/O, and memory). The memory-mapped PCI spaces are described in
“Processor Core Access to PCI Space” on page 13-3 . This section
describes the memory-mapped control and status registers.
There are two sets of memory-mapped registers (MMRs) on the
ADSP-BF535 processor. The control and status registers clocked in the
internal ADSP-BF535 processor system clock domain are mapped into the
system MMR space. The control and status registers clocked in the PCI
clock domain are mapped into the PCI Configuration Registers memory
range (see the PCI memory map in
Figure 13-2 on page 13-5 ). Each
group of registers is described in the sections that follow.
Bus Operation Ordering
Processor core accesses to the PCI interface always occur in the order that
the processor core initiated the system access. This implies:
• Since the processor core allows reads to occur before writes, with
respect to instruction order, the programmer must explicitly order
the load and store instruction by inserting an
SSYNC
instruction
between them in the cases where a PCI read must see the effect of a
previous PCI write. This is not required if the load and store
address and size are the same, for example, a write to a PCI Status
register followed by a read from the same register.
• ADSP-BF535 processor hardware does not enforce ordering among
the EAB, PAB, and EMB buses. Software must explicitly manage
any coherency issues among these buses. Shared resources should
be protected by software locks. With respect to program order,
EAB reads and PAB accesses are always completed in order, since
the core is stalled until they complete.