Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-25
Memory
• Execute the code of interest. Any cacheable exceptions, such as exit
code, traversed by this code execution are also locked into the
instruction cache.
• Upon exit of the critical code, clear
ILOC[3:1]
, and set
ILOC[0]
.
The critical code (and the instructions which set
ILOC[0]
), are now
locked into Way0.
• Re-enable interrupts, if required.
If all four Ways of the cache are locked, then further allocation into the
cache is prevented.
Instruction Cache Invalidation
The
IFLUSH
instruction can explicitly invalidate cache lines based on their
tag addresses. The target address of the instruction is generated from the
P-registers. Because the instruction cache never contains modified (dirty)
data, the cache line is simply invalidated.
In the following example, the
P2
register contains the address of a valid
memory location. If this address has been brought into cache, the corre-
sponding cache line is invalidated after the execution of this instruction.
Example of
ICACHE
instruction:
iflush [ p2 ] ; /* Invalidate cache line containing address
that P2 points to */
Because the
IFLUSH
instruction is used to invalidate a specific address in
the ADSP-BF535 processor memory map, it is impractical to use this
instruction to invalidate an entire bank of cache. A second, faster tech-
nique can be used to invalidate an entire cache bank directly. This second
technique directly invalidates Valid bits, which are in a random state when
the ADSP-BF535 processor comes out of reset; it sets the Valid bit of each
cache line to the invalid state. To implement this technique, additional
MMRs are available to allow arbitrary read/write of all cache entries
directly.