Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 764 / 1022

SDRAM Controller (SDC)
18-40 ADSP-BF535 Blackfin Processor Hardware Reference
The
SCTLE
bit is used to enable or disable the SDC. If
SCTLE
is disabled,
any access to SDRAM address space generates an internal bus error, and
the access does not occur externally.
For more information, see “Error
Detection” on page 18-8. When
SCTLE
is disabled, all SDC control pins
are in their inactive states and the SDRAM clock is not running. The
SCTLE
bit must be enabled for SDC operation.
To support higher clock load requirements, two SDRAM clock pins
(
SCLK[0]
and
SCLK[1]
) are provided. The clock timing of these two pins is
identical, and the clock load on
SCLK[0]
and
SCLK[1]
should be balanced.
SCLK[0]
runs whenever the SDC is enabled (
SCTLE = 1
).
SCLK[1]
runs
whenever
SCK1E
is enabled. Both the
SCTLE
and
SCK1E
bits are enabled dur-
ing reset, so
SCLK[0]
and
SCLK[1]
are running after reset deasserts. If the
SDC will not be used, the
SCTLE
and
SCK1E
bits can be disabled to stop the
clocks and reduce power dissipation. Even though the SDC is enabled
(
SCTLE = 1
) at reset, the power-up sequence (
PSSE = 1
) must be executed
before reading or writing to SDRAM address space.

Failure to execute the power-up sequence before reading or writing
to SDRAM address space results in unpredictable operation.
The CAS latency (
CL
), SDRAM t
RAS
timing (
TRAS
), SDRAM t
RP
timing
(
TRP
), SDRAM t
RCD
timing (
TRCD
), and SDRAM t
WR
timing (
TWR
) bits
should be programmed based on the system clock frequency and the tim-
ing specifications of the SDRAM used. Note that all SDRAM banks use
the same timing. All timing parameters must be written with valid values
based on the clock frequency and the timing specifications of the SDRAM
before any access to SDRAM address space, including the power-up
sequence.