Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 2-43
Computational Units
The instruction takes multiple cycles to execute. Refer to the product data
sheet and
Blackfin Processor Programming Reference for more information
about the exact operation of this instruction. This ‘macro’ function is
interruptable and does not modify the data in either accumulator register
A0
or
A1
.
Dual MAC Operations
The ADSP-BF535 processor has two 16-bit MACs. Both MACs can be
used in the same operation to double the MAC throughput. The same two
32-bit input registers are offered to each MAC unit, providing each with
four possible combinations of 16-bit input operands. Dual MAC opera-
tions are frequently referred to as
Vector operations, because a program
could store vectors of samples in the four input operands and perform vec-
tor computations.
An example of a dual multiply and accumulate instruction is
A1 += R1.H * R2.L, A0 += R1.L * R2.H ;
This instruction represents two multiply and accumulate operations:
• In one operation, in MAC1, the high half of
R1
is multiplied by the
low half of
R2
and added to the contents of the
A1
accumulator.
• In the second operation, in MAC0, the low half of
R1
is multiplied
by the high half of
R2
and added to the contents of
A0
.
The results of the MAC operations may be written to registers in a num-
ber of ways: as a pair of 16-bit halves, as a pair of 32-bit registers, or as an
independent 16-bit half register or 32-bit register.
For example:
R3.H = ( A1 += R1.H * R2.L ), R3.L = ( A0 += R1.L * R2.L ) ;