Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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G-20 ADSP-BF535 Blackfin Processor Hardware Reference
page size.
The amount of memory which has the same row address and can be
accessed with successive read or write commands without needing to
activate another row. The page size can be calculated for 32-bit and 16-bit
SDRAM banks with these formulas:
• 32-bit SDRAM banks: page size = 2
(CAW + 2)
• where
CAW
is the column address width of the SDRAM, plus 2
because the SDRAM bank is 32 bits wide (2 address bits = 4 bytes).
• 16-bit SDRAM banks: page size = 2
(CAW + 1)
• where
CAW
is the column address width of the SDRAM, plus 1
because the SDRAM bank is 16 bits wide (1 address bit = 2 bytes).
PC (Program Counter).
A register that contains the address of the next instruction to be executed.
The PC is automatically incremented after each instruction is fetched to
point to the following instruction.
PCI.
See Peripheral Component Interconnect
peripheral.
The ADSP-BF535 processor’s peripherals include timers, Real-Time
Clock, USB, programmable flags, UARTs, SPORTs, and SPIs.
Peripheral Access Bus (PAB).
A low and predictable latency bus that keeps core stalls to a minimum and
allows for manageable interrupt latencies to time critical peripherals.