Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Timer Modes
16-18 ADSP-BF535 Blackfin Processor Hardware Reference
Pulse Width Count and Capture Mode (WDTH_CAP)
In WDTH_CAP mode, the
TMRx
pin is an input pin. The internally
clocked timer is used to determine the period and pulse width of
externally applied rectangular waveforms. Setting the
MODE_FIELD
bit in
TIMERx_CONFIG
to b#10 enables this mode. The period and width registers
are read-only in WDTH_CAP mode.
When enabled in this mode, the timer resets the value in the
TIMERx_COUNTER
register to 0x0000 0001 and does not start counting until
it detects the leading edge on the
TMRx
pin.
When the timer detects a first leading edge, it starts incrementing. When
it detects the trailing edge of a waveform, the timer captures the current
32-bit value of
TIMERx_COUNTER
into
TIMERx_WIDTH
. At the next leading
edge, the timer transfers the current 32-bit value of
TIMERx_COUNTER
into
TIMERx_PERIOD
. The
TIMERx_COUNTER
register is reset to 0x0000 0001, and
the timer continues counting until it is either disabled or the count value
reaches 0xFFFF FFFF.
In WDTH_CAP mode, software can simultaneously measure both the
pulse width and the pulse period of a waveform. To control the definition
of leading edge and trailing edge of the
TMRx
pin, the
PULSE_HI
bit in
TIMERx_CONFIG
is set or cleared. If the
PULSE_HI
bit is cleared, the mea-
surement is initiated by a falling edge, the value in the
TIMERx_COUNTER
register is captured to the
TIMERx_WIDTH
register on the rising edge, and
the period is captured on the next falling edge.

With
IRQ_ENA
set, the width registers become sticky in
WDTH_CAP mode. Once a pulse width event (trailing edge) has
been detected and properly latched, the width registers do not
update anymore unless the
IRQx
bit is cleared by software. The
period registers still update every time a leading edge is detected.