Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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UARTx Control and Status Registers
12-12 ADSP-BF535 Blackfin Processor Hardware Reference
Note the 16-bit divisor resets to 0x0001 resulting in the highest possible
clock frequency by default. If the UART is not used, changing the value of
this register may help save power.
Table 12-9 provides example divide factors required to support most stan-
dard baud rates.

Careful selection of
SCLK
frequencies, that is, even multiples of
desired baud rates, can result in lower error percentages.
UARTx Modem Control Registers (UARTx_MCR)
The
UARTx_MCR
register contains modem control and test signals, as shown
in Figure 12-9 .
Loopback mode forces the TX pin to high and disconnects the RX pin
from the Receive Shift register (
RSR
), so the
RSR
input is directly connected
to the Transmit Shift register (
TSR
) output. When Loopback mode is
enabled, modem control signals in the UARTx Modem Control Register
Table 12-9. UART Baud Rate Examples with 100 MHz SCLK
Baud Rate DL Actual % Error
2400 2604 2400.15 .006
4800 1302 4800.31 .007
9600 651 9600.61 .006
19200 326 19171.78 .147
38400 163 38343.56 .147
57600 109 57339.45 .452
115200 54 115740.74 .469
921600 7 892857.14 3.119
6250000 1 6250000 -