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SPI Transfer Formats

10-28

ADSP-BF535 Blackfin Processor Hardware Reference

SPI Transfer Formats

The ADSP-BF535 SPI supports four different combinations of serial clock
phase and polarity, selectable using the

CPOL

and

CPHA

bits in

SPIx_CTL

.

The SPI transfer protocols shown in

Figure 10-18

and

Figure 10-19

dem-

onstrate the two basic transfer formats as defined by the

CPHA

bit. Two

waveforms are shown for

SCK

: one for

CPOL = 0

and the other for

CPOL =

1

. The diagrams may be interpreted as master or slave timing diagrams

since the

SCK

,

MISO

, and

MOSI

pins are directly connected between the mas-

ter and the slave. The

MISO

signal is the output from the slave (slave

transmission), and the

MOSI

signal is the output from the master (master

transmission). The

SCK

signal is generated by the master, and the

SPISS

signal is the slave device select input to the slave from the master. The dia-
grams represent an 8-bit transfer (

SIZE = 0

) with MSB first (

LSBF = 0

).

Any combination of the

SIZE

and

LSBF

bits of

SPIx_CTL

is allowed. For

example, a 16-bit transfer with LSB first is another possible configuration.

The clock polarity and the clock phase should be identical for the master
device and the slave device involved in the communication link. The
transfer format from the master may be changed between transfers to
adjust to various requirements of a slave device.

SPIx_DESCR_RDY

SPI port DMA
descriptor ready

Write a 1 to bit 0 to reactivate a descriptor
fetch

SPIx_DMA_INT

SPI port interrupt
status

All three Interrupt Status bits are sticky;
write a 1 to the corresponding bit to clear

Table 10-18. SPI Register Mapping (Cont’d)

Register Name

Function

Notes

«
...
432
433
434
435
436
...
»

Summary of Contents for ADSP-BF535 Blackfin

Page 1: ...a ADSP BF535 Blackfin Processor Hardware Reference Revision 3 3 February 2013 Part Number 82 000410 13 Analog Devices Inc One Technology Way Norwood Mass 02062 9106...

Page 2: ...ed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No...

Page 3: ...ew in This Manual xlviii Technical Support xlviii Supported Processors xlix Product Information l Analog Devices Web Site l EngineerZone li Notation Conventions lii Register Diagram Conventions liii I...

Page 4: ...unction 1 14 PCI Target Function 1 15 USB Port 1 15 Real Time Clock 1 15 Watchdog Timer 1 16 Timers 1 17 Serial Ports SPORTs 1 17 Serial Peripheral Interface SPI Ports 1 19 UART Ports 1 20 Programmabl...

Page 5: ...ers Two s Complement 2 4 Fractional Representation 1 15 2 4 Register Files 2 5 Data Register File 2 6 Accumulator Registers 2 6 Pointer Register File 2 6 DAG Register Set 2 7 Register File Instruction...

Page 6: ...Single 16 Bit Operations 2 25 Dual 16 Bit Operations 2 25 Quad 16 Bit Operations 2 25 Single 32 Bit Operations 2 27 Dual 32 Bit Operations 2 27 ALU Instruction Summary 2 28 ALU Data Flow Details 2 28...

Page 7: ...l 32 Bit Integer MAC Instruction 2 42 Dual MAC Operations 2 43 Barrel Shifter Shifter 2 44 Shifter Operations 2 44 Two Operand Shifts 2 45 Immediate Shifts 2 45 Register Shifts 2 46 Three Operand Shif...

Page 8: ...e State 3 9 Example Code for Transition to Idle State 3 10 Reset State 3 10 System Reset and Power up Configuration 3 12 Hardware Reset 3 13 System Reset Configuration Register SYSCR 3 14 Software Res...

Page 9: ...oops and Sequencing 4 15 Events and Sequencing 4 17 System Interrupt Processing 4 20 System Peripheral Interrupts 4 22 System Interrupt Wakeup Enable Register SIC_IWR 4 24 System Interrupt Status Regi...

Page 10: ...4 46 Interrupts With and Without Nesting 4 48 Example Prolog Code for Nested Interrupt Service Routine 4 51 Example Epilog Code for Nested Interrupt Service Routine 4 51 Logging of Nested Interrupt Re...

Page 11: ...Addressing 5 10 Pre Modify Stack Pointer Addressing 5 11 Indexed Addressing With Immediate Offset 5 11 Post Modify Addressing 5 11 Modifying DAG and Pointer Registers 5 12 Memory Address Alignment 5 1...

Page 12: ...6 22 Cache Line Replacement 6 22 Instruction Cache Management 6 24 Instruction Cache Locking 6 24 Instruction Cache Invalidation 6 25 Instruction Test Registers 6 26 Instruction Test Command Register...

Page 13: ...ess 6 52 Latency 6 53 Off Chip L2 Memory 6 55 Memory Protection and Properties 6 56 Memory Management Unit 6 56 Memory Pages 6 58 Memory Page Attributes 6 58 Page Descriptor Table 6 60 CPLB Management...

Page 14: ...del 6 76 Load Store Operation 6 77 Interlocked Pipeline 6 78 Ordering of Loads and Stores 6 79 Synchronizing Instructions 6 80 Speculative Load Execution 6 81 Conditional Load Behavior 6 82 Working Wi...

Page 15: ...gents Masters 7 14 External Access Bus EAB 7 14 EAB Arbitration 7 15 EAB Performance 7 15 EAB Bus Agents Masters Slaves 7 17 External Mastered Bus EMB 7 18 EMB Arbitration 7 18 EMB Performance 7 18 EM...

Page 16: ...Mode 8 12 Active Mode 8 12 Sleep Mode 8 13 Deep Sleep Mode 8 14 Operating Mode Transitions 8 14 Programming Operating Mode Transitions 8 17 PLL Programming Sequence 8 17 PLL Programming Sequence Cont...

Page 17: ...Peripheral DMA Transfer Count Register 9 19 Peripheral DMA Start Address Registers 9 21 Peripheral DMA Next Descriptor Pointer Register 9 23 DMA Descriptor Base Pointer Register DMA_DBP 9 24 Periphera...

Page 18: ...Configuration Register MDS_DCFG 9 39 Source Memory DMA Transfer Count Register MDD_DCT 9 40 Source Memory DMA Start Address Registers MDS_DSAH MDS_DSAL 9 41 Source Memory DMA Next Descriptor Pointer R...

Page 19: ...Ix_BAUD 10 7 SPIx Control Register SPIx_CTL 10 8 SPIx Flag Register SPIx_FLG 10 10 Slave Select Inputs 10 13 Multiple Slave SPI Systems 10 14 SPIx Status Register SPIx_ST 10 15 SPIx Transmit Data Buff...

Page 20: ...I Transfer Formats 10 28 SPI General Operation 10 30 Clock Signals 10 31 Master Mode Operation 10 32 Transfer Initiation From Master Transfer Modes 10 33 Slave Mode Operation 10 34 Slave Ready for a T...

Page 21: ...x_STAT Registers 11 24 SPORTx Multichannel Transmit Select SPORTx_MTCSx Registers 11 26 SPORTx Multichannel Receive Select SPORTx_MRCSx Registers 11 28 SPORTx Multichannel Configuration SPORTx_MCMCx R...

Page 22: ...ss High SPORTx_START_ADDR_HI_TX Registers 11 44 SPORTx Transmit DMA Start Address Low SPORTx_START_ADDR_LO_TX Registers 11 45 SPORTx Transmit DMA Count SPORTx_COUNT_TX Registers 11 46 SPORTx Transmit...

Page 23: ...Versus Late Frame Syncs Normal Versus Alternate Timing 11 58 Data Independent Transmit Frame Sync 11 60 Multichannel Operation 11 61 Frame Syncs In Multichannel Mode 11 63 Multichannel Frame Delay 11...

Page 24: ...e Buffer Registers UARTx_RBR 12 6 UARTx Interrupt Enable Registers UARTx_IER 12 7 UARTx Interrupt Identification Registers UARTx_IIR 12 9 UARTx Divisor Latch Registers UARTx_DLL UARTx_DLH 12 10 UARTx...

Page 25: ...X 12 26 UARTx Receive DMA IRQ Status Registers UARTx_IRQSTAT_RX 12 27 UART DMA Transmit Registers 12 27 UARTx Transmit DMA Current Descriptor Pointer Registers UARTx_CURR_PTR_TX 12 28 UARTx Transmit D...

Page 26: ...n 13 3 PCI Host Function 13 3 Processor Core Access to PCI Space 13 3 External PCI Requirements 13 4 Device Mode Operation 13 4 Outbound Transactions ADSP BF535 Processor as PCI Initiator 13 6 General...

Page 27: ...trol and Status Registers 13 19 PCI Bridge Control Register PCI_CTL 13 20 PCI Status Register PCI_STAT 13 21 PCI Interrupt Controller Register PCI_ICTL 13 22 PCI Outbound Memory Base Address Register...

Page 28: ...CI_CFG_HT 13 36 PCI Configuration Memory Latency Timer Register PCI_CFG_MLT 13 36 PCI Configuration Cache Line Size Register PCI_CFG_CLS 13 37 PCI Configuration Memory Base Address Register PCI_CFG_MB...

Page 29: ...ality 14 2 USB Requirements 14 3 Master and Slave Buses 14 3 Data Flow and Traffic Scheduling 14 4 USB Implementation 14 4 Block Diagram 14 6 UDC Block 14 6 Front End Interface Block 14 7 Clock Contro...

Page 30: ...Register USBD_ID 14 16 Current USB Frame Number Register USBD_FRM 14 17 Match Value for USB Frame Number Register USBD_FRMAT 14 18 Enable Download of Configuration Into UDC Core Register USBD_EPBUF 14...

Page 31: ...Endpoint x Control Registers USBD_EPCFGx 14 31 USB Endpoint x Address Offset Registers USBD_EPADRx 14 33 USB Endpoint x Buffer Length Registers USBD_EPLENx 14 34 UDC Endpoint Buffer Register 14 35 In...

Page 32: ...ete 14 42 USBD_BCSTAT Buffer Complete 14 43 USBD_SETUP Setup Packet Received 14 43 USBD_MSETUP Multiple Setup Packets Received 14 43 USBD_MERR Memory Controller Error 14 43 USB Programming Model 14 44...

Page 33: ...etection 14 61 Reset Signaling Detected on USB 14 61 Suspend Resume Considerations 14 62 References 14 62 PROGRAMMABLE FLAGS Programmable Flag Memory Mapped Registers MMRs 15 2 Flag Direction Register...

Page 34: ..._COUNTER 16 11 Timer Modes 16 13 Pulse Width Modulation Mode PWM_OUT 16 13 Pulse Width Modulation PWM Waveform Generation 16 14 Single Pulse Generation 16 17 Pulse Width Count and Capture Mode WDTH_CA...

Page 35: ...Register RTC_ICTL 17 8 RTC Interrupt Status Register RTC_ISTAT 17 9 RTC Stopwatch Count Register RTC_SWCNT 17 10 RTC Alarm Register RTC_ALARM 17 11 RTC Enable Register RTC_FAST 17 12 EXTERNAL BUS INTE...

Page 36: ...Asynchronous Accesses by MemDMA 18 23 Asynchronous Reads 18 24 Asynchronous Writes 18 26 Adding Additional Wait States 18 26 SDRAM Controller SDC 18 28 Definition of Terms 18 29 SDRAM Memory Global C...

Page 37: ...Address Decode 18 56 SDRAM Address Mapping 18 59 32 Bit Wide SDRAM Address Muxing 18 60 16 Bit Wide SDRAM Address Muxing 18 65 Data Mask SDQM 3 0 Encodings 18 68 SDC Operation 18 70 SDC Configuration...

Page 38: ...Clock Pins 19 3 Configuring and Servicing Interrupts 19 5 Semaphores 19 6 Example Code for Query Semaphore 19 7 Data Delays Latencies and Throughput 19 8 Bus Priorities 19 8 PCI Arbiter 19 8 USB Devi...

Page 39: ...ess Count Registers WPIACNTx 20 6 Watchpoint Instruction Address Control Register WPIACTL 20 7 Data Address Watchpoints 20 10 Watchpoint Data Address Registers WPDAx 20 11 Watchpoint Data Address Coun...

Page 40: ...egisters 20 25 Chip ID Register CHIPID 20 26 DSP Device ID Register DSPID 20 27 DMA Bus Debug Registers 20 27 DMA Bus Control Comparator Register DB_CCOMP 20 28 DMA Bus Address Comparator Register DB_...

Page 41: ...Controller Registers B 5 UART1 Controller Registers B 8 Timer Registers B 11 Programmable Flag Registers B 13 SPORT0 Controller Registers B 14 SPORT1 Controller Registers B 19 SPI0 Controller Register...

Page 42: ...C 6 EXTEST Binary Code 00000 C 6 SAMPLE PRELOAD Binary Code 10000 C 6 IDCODE Binary Code 00010 C 7 BYPASS Binary Code 11111 C 7 Boundary Scan Register C 8 NUMERIC FORMATS Unsigned or Signed Two s Comp...

Page 43: ...or programming information see Blackfin Processor Programming Refer ence For timing electrical and package specifications see ADSP BF535 Blackfin Embedded Processor Data Sheet Intended Audience The pr...

Page 44: ...rating modes of the ADSP BF535 proces sor Emulation mode Supervisor mode and User mode The chapter also describes Idle state and Reset state Chapter 4 Program Sequencer Describes the operation of the...

Page 45: ...y Access Describes the channel DMA and Memory DMA controllers The channel DMA section discusses direct block data movements between a peripheral with DMA access and internal or external memory spaces...

Page 46: ...f the USBD as well as descriptions of the USBD registers interrupts and programming model Chapter 15 Programmable Flags Describes the programmable flags or general purpose I O pins in the ADSP BF535 p...

Page 47: ...ssor s Debug Describes the Blackfin processor debug functionality which can be used for software debugging and complements some services often found in an operating system Appendix A Blackfin Processo...

Page 48: ...e STOPCK bit in Chapter 8 Dynamic Power Management Description of multichannel mode operation in Chapter 11 Serial Port Controllers Note on timing dependencies for the TRP and TRAS settings in the EBI...

Page 49: ...about processors and processor applications to processor support analog com or processor china analog com Greater China support In the USA only call 1 800 ANALOGD 1 800 262 5643 Contact your Analog D...

Page 50: ...related to the product as well as a link to the previous revisions of the manuals When locating your manual title note a possible errata check mark next to the title that leads to the current correcti...

Page 51: ...nical support engineers You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions Use EngineerZone to connect with other DSP developers wh...

Page 52: ...terminated with an ellipsis read the example as an optional comma separated list of this SECTION Commands directives keywords and feature names are in text with letter gothic font filename Non keywor...

Page 53: ...ster do not follow the overall read write con vention this is noted in the bit description after the bit name If a bit has a short name the short name appears first in the bit description followed by...

Page 54: ...state of PULSE_HI alternates each period 00 No error 01 Counter overflow error 10 Period register programming error 11 Pulse width register programming error 00 Reset state unused 01 PWM_OUT mode 10...

Page 55: ...power consumption than other DSPs Throughout this manual the words core and system are used to describe sections of the ADSP BF535 processor The word core denotes the processor L1 memory Event Control...

Page 56: ...transfers among the various chip memory spaces including external synchronous dynamic random access memory SDRAM and asynchronous memory and internal Level 2 SRAM and PCI memory spaces Multiple on ch...

Page 57: ...ata and perform shifting rotating normal ization and extraction operations Data for the computational units is located in a multiported register file of sixteen 16 bit entries or eight 32 bit entries...

Page 58: ...s provide addresses for simultaneous dual operand fetches from memory The DAGs share a register file con taining four sets of 32 bit Index Modify Length and Base registers Eight additional 32 bit regi...

Page 59: ...access The architecture provides three modes of operation User Supervisor and Emulation User mode has restricted access to a subset of system resources thus providing a protected software environment...

Page 60: ...128 MB SDRAM Memory Bank 0 16 MB 128 MB 0xEEFF FFFC 0xEEFF FF00 0xEEFE FFFF 0xEEFE 0000 0xE7FF FFFF 0xE000 0000 0x2FFF FFFF 0x2C00 0000 0x2800 0000 0x2400 0000 0x2000 0000 0x1800 0000 0x1000 0000 0x0...

Page 61: ...emory consisting of 16 Kbytes of 4 way set asso ciative cache memory In addition the memory may be configured as an SRAM This memory is accessed at full processor speed L1 data memory consisting of tw...

Page 62: ...rogrammed to inter face with up to four banks of SDRAM Each bank contains between 16 Mbytes and 128 Mbytes providing access to up to 512 Mbytes of RAM Each bank can be programmed independently and is...

Page 63: ...tions this window anywhere in the 4 Gbyte PCI memory space while its position with respect to the processor addresses remains fixed The PCI I O region is also a 4 Gbyte space however most systems and...

Page 64: ...ls as well as external devices accessing resources through the PCI bus The system MMRs are accessible by the core in Supervisor mode and can be mapped as either visible or reserved to other devices de...

Page 65: ...is triggered the state of the processor is saved on the kernel stack The ADSP BF535 processor event controller consists of two stages the Core Event Controller CEC and the System Interrupt Controller...

Page 66: ...tination enabling access to the entire Blackfin address space In addition to the dedicated peripheral DMA channels there is a separate memory DMA channel provided for transfers between the various ADS...

Page 67: ...memory controller provides a configurable interface for up to four separate banks of memory or I O devices Each bank can be independently programmed with different timing parameters This allows conne...

Page 68: ...ADSP BF535 processor is the host The three PCI address spaces memory I O and configuration space are mapped into the ADSP BF535 flat 32 bit memory space Since the PCI memory space is as large as the...

Page 69: ...Control Bulk Interrupt and Isochronous Each endpoint provides a memory mapped buffer for transferring data to the application The ADSP BF535 USB port has a dedicated DMA controller and interrupt input...

Page 70: ...which can be used to implement a software watchdog function A software watchdog can improve system availability by forcing the processor to a known state via generation of a hardware reset non maskabl...

Page 71: ...synchronization either to the processor clock or to a count of external signals In addition to the three general purpose programmable timers a fourth timer is also provided This extra timer is clocke...

Page 72: ...s a wide range of frequencies Word length Each SPORT supports serial data words from 3 to 16 bits in length transferred in most significant bit first or least signif icant bit first format Framing Eac...

Page 73: ...le with the H 100 H 110 MVIP 90 and HMVIP standards Serial Peripheral Interface SPI Ports The ADSP BF535 processor has two SPI compatible ports that enable the processor to communicate with multiple S...

Page 74: ...er peripherals or hosts They provide full duplex DMA supported asynchronous transfers of serial data Each UART port includes support for 5 to 8 data bits 1 or 2 stop bits and none even or odd parity T...

Page 75: ...erate an interrupt When a PF pin is configured as an input an interrupt can be generated according to the state of the pin high or low an edge transition low to high or high to low or on both edge tra...

Page 76: ...nce can be achieved The processor core and all enabled peripherals run at full speed Active Operating Mode Low Power Savings In the Active mode the PLL is enabled but bypassed The input clock is used...

Page 77: ...own mode can only be exited by assertion of the reset interrupt or by an interrupt generated by the RTC Clock Signals The ADSP BF535 processor can be clocked by a sine wave input or a buff ered shaped...

Page 78: ...ssembly language instruction set uses an algebraic syntax that compiles to a small final memory size The set also provides multifunction instructions that allow the programmer to use many of the proce...

Page 79: ...et board processor during emulation The emulator provides full speed emulation allowing inspection and modification of memory registers and processor stacks Nonintrusive in circuit emulation is assure...

Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...

Page 81: ...e shifter executes logical shifts and arithmetic shifts and performs bit packing and extraction The video ALUs perform single instruction multiple data SIMD logical operations on specific 8 bit data o...

Page 82: ...tion instructions Figure 2 1 shows the relationship between the ADSP BF535 Data Regis ter File and computational units multipliers ALUs and shifter Figure 2 1 ADSP BF535 Core Architecture SP SEQ UENCE...

Page 83: ...ng Data Formats Blackfin processors are primarily 16 bit fixed point machines Most oper ations assume a two s complement number representation while others assume unsigned numbers or simple binary str...

Page 84: ...tions presume or support two s complement arithmetic Fractional Representation 1 15 Blackfin processor arithmetic is optimized for numerical values in a frac tional binary format denoted by 1 15 one d...

Page 85: ...Pointer Register File has pointers for addressing operations The DAG registers are dedicated registers that manage zero over head circular buffers for DSP operations For more information see Data Add...

Page 86: ...garded as two independent register halves R0 L and R0 H Two separate buses connect the register file to the L1 data memory each bus being 32 bits wide Transfers between the Data Register File and the...

Page 87: ...ssing The DAG register set consists of these registers I 3 0 contain index addresses M 3 0 contain modify values B 3 0 contain base addresses L 3 0 contain length values All DAG registers are 32 bits...

Page 88: ...es A0 or A1 Dreg denotes any Data Register File register Sysreg denotes ASTAT SEQSTAT SYSCFG RETI RETX RETN RETE or RETS LC 1 0 LT 1 0 LB 1 0 EMUDAT CYCLES and CYCLES2 Preg denotes any Pointer registe...

Page 89: ...ruction Indicates the flag is cleared Indicates no effect Table 2 1 Register File Instruction Summary Instruction ASTAT Status Flags AZ AN AC0 AC1 AV0 AV0S AV1 AV1S CC V VS allreg allreg 1 An An An Dr...

Page 90: ...ter d repre sents one bit and the letter s represents one signed bit Some instructions manipulate data in the registers by sign extending or zero extending the data to 32 bits Instructions zero extend...

Page 91: ...a source other than adjacent bits Table 2 2 Data Formats Format Representation in Memory Representation in 32 Bit Register 32 0 Unsigned Word dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dd...

Page 92: ...ing on the transfer of the result from both accumulators to the reg ister file Furthermore the sticky VS bit is set with the V bit and remains set until cleared 1 15 Signed Fraction s ddd dddd dddd dd...

Page 93: ...status information For more information about using ALU status see ALU Instruction Summary on page 2 28 Multiplier Data Types Each multiplier produces results that are binary strings The inputs are in...

Page 94: ...ltiplier results generate status information when they are transferred to a destination register in the register file For more information see Mul tiplier Instruction Summary on page 2 35 Shifter Data...

Page 95: ...gned Same as operands Table 2 4 Multiplier Fractional Modes Formats Operation Operand Formats Result Formats Multiplication 1 15 explicitly signed or unsigned 2 30 shifted to 1 31 Multiplication addit...

Page 96: ...the product lines up with bit 1 of A0 which is bit 1 of A0 W The LSB is zero filled The fractional multi plier result format appears in Figure 2 4 For integer arithmetic the 32 bit product register is...

Page 97: ...1 1 1 0 9 8 7 6 5 4 3 2 1 0 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 P SIGN 7 BITS MULTIPLIER P OUTPUT A0 X A0 W SHIFTED OUT ZERO FILLE...

Page 98: ...ost algorithms unbiased rounding is preferred Unbiased Rounding The convergent rounding method returns the number closest to the origi nal In cases where the original number lies exactly halfway betwe...

Page 99: ...ero has the effect of rounding odd A0 L A1 L values upward and even values down ward yielding a zero large sample bias assuming uniformly distributed values The following examples use x to represent a...

Page 100: ...en 0 5 and 0 0 binary 0 0 so this method rounds up Because it always rounds up this method is called biased rounding The RND_MOD bit in the ASTAT register enables biased rounding When the RND_MOD bit...

Page 101: ...a relatively large bias Instructions that do not support rounding revert to truncation The RND_MOD bit in ASTAT has no effect on truncation Special Rounding Instructions The ALU provides the ability...

Page 102: ...performs an addition of two 32 bit numbers biased rounding at bit 20 depositing the result in a half word Using Computational Status The multiplier ALU and shifter update the overflow and other status...

Page 103: ...X X X X X Arithmetic Status Register ASTAT 0 Last result written to A0 has not overflowed 1 Last result written to A0 has overflowed AV0 A0 Overflow Reset Undefined 0 Last result written to A1 has no...

Page 104: ...ogical AND OR NOT XOR bitwise XOR Negate Functions ABS MAX MIN Round division primitives ALU Operations Primary ALU operations occur on ALU0 while parallel operations occur on ALU1 which performs a su...

Page 105: ...the input to the ALU considered as pairs of 16 bit operands An addition subtraction or logical operation produces two 16 bit results that are deposited into an arbitrary 32 bit destination register AL...

Page 106: ...d input operands must be the same for both ALUs For example R3 R0 R1 R2 R0 R1 S performs four operations Adds the 16 bit contents of R1 H R1 high half to the 16 bit con tents of the R0 H R0 high half...

Page 107: ...P FP Instructions may not intermingle Pointer registers with Data registers For example R3 R1 R2 NS adds the 32 bit contents of R2 to the 32 bit contents of R1 and deposits the result in R3 with no sa...

Page 108: ...information about assembly language syntax and the effect of ALU instructions on the status flags see Appendix A ADSP BF535 Consider ations in the Blackfin Processor Programming Reference ALU Data Flo...

Page 109: ...paired providing four possible combinations of addition and subtraction A H H L L B H H L L C H H L L D H H L L Figure 2 10 Register Files and ALUs MAC0 SHIFTER MAC1 32b 32b 32b 32b 32b OPERAND FROM...

Page 110: ...laced in the high half of the result register and the result from the low side calculation is placed in the low half of the result register With the cross option the high result is placed in the low h...

Page 111: ...flags see Appendix A ADSP BF535 Consider ations in the Blackfin Processor Programming Reference Depending on the instruction the inputs can come from the Data Regis ter File the Pointer Register File...

Page 112: ...are presented to the Video ALUs in two 32 bit words from the Data Register File The possible operations include Byte alignment Quad byte sum absolute differences Quad byte averaging Quad byte pack and...

Page 113: ...0 The accumulator results can be saturated to 32 or 40 bits The multiplier result can also be written directly to a 16 or 32 bit destination register with optional rounding Each multiplier instruction...

Page 114: ...in the Data Register File Rounding or Saturating Multiplier Results On a multiply and accumulate operation the accumulator data can be sat urated and optionally rounded for extraction to a register o...

Page 115: ...and the effect of multi plier instructions on the status flags see Appendix A ADSP BF535 Considerations in the Blackfin Processor Programming Reference Multiplier Instruction Options The following des...

Page 116: ...alue larger than 32 bits the number is satu rated to its maximum positive or negative value S2RND If multiplying and accumulating to a half register Input data operands are signed fraction When copyin...

Page 117: ...rounded then copied into the des tination half register W32 Input data operands are signed fraction with no extension bits in the Accumulators at 32 bits Left shift correction of the product is perfor...

Page 118: ...n and stores the result in a 40 bit accumulator or extracts to a 16 bit or 32 bit register Two 32 bit words are available at the MAC inputs provid ing four 16 bit operands to chose from Figure 2 13 Re...

Page 119: ...14 show these possible combinations The 32 bit product is passed to a 40 bit adder subtracter which may add or subtract the new product from the contents of the accumulator result register or pass the...

Page 120: ...red in a register from the Data Register File or the Accumulator register The destination register may be 16 bits or 32 bits If a 16 bit destination register is a low half then MAC0 is used if it is a...

Page 121: ...registers These extractions provide the most useful information in the resul tant 16 bit word for the data type chosen see Figure 2 16 This example uses fractional unsigned operands R0 L R1 L R2 L FU...

Page 122: ...cial 32 Bit Integer MAC Instruction The ADSP BF535 processor supports a multicycle 32 bit MAC instruc tion that is Dreg Dreg The single instruction multiplies two 32 bit integer operands and provides...

Page 123: ...operands Dual MAC opera tions are frequently referred to as Vector operations because a program could store vectors of samples in the four input operands and perform vec tor computations An example o...

Page 124: ...ter pairs R 1 0 R 3 2 R 5 4 R 7 6 R3 H A1 R1 H R2 L A0 R1 L R2 L This instruction is an example of one accumulator but not the other being transferred to a register Either a 16 or 32 bit register may...

Page 125: ...ic shift logical shift and rotate instructions can obtain the shift argument from a register or directly from an immediate value in the instruction For details about shifter related instructions see S...

Page 126: ...rive the shift value and when the magnitude of the shift is greater than 32 then the result is either 0 or 1 The following example shows the input value up shifted R0 0x0000 B6A3 R2 0x0000 0004 R0 R2...

Page 127: ...value When a register is used to hold the shift value for ASHIFT LSHIFT or ROT then the shift value is always found in the low half of a register Rn L The bottom 6 bits of Rn L are masked off and used...

Page 128: ...R R0 6 BITSET R2 9 BITTGL R3 2 CC BITTST R3 0 Field Extract and Field Deposit If the shifter is used a source field may be deposited anywhere in a 32 bit destination field The source field may be from...

Page 129: ...ain of application programs Supervisor mode and Emulation mode are usually reserved for the kernel code of an operating system The processor mode is determined by the Event Controller When servic ing...

Page 130: ...e IPEND Interrupt Supervisor 0x10 but IPEND 0 IPEND 1 IPEND 2 and IPEND 3 0 Exception Supervisor 0x08 The core is processing an exception event if IPEND 0 0 IPEND 1 0 IPEND 2 0 IPEND 3 1 and IPEND 15...

Page 131: ...pt to access restricted system registers causes an exception event Table 3 2 lists the registers that may be accessed in User mode Figure 3 1 Processor Modes and States Interrupt RTI Event EMULATION S...

Page 132: ...in Table 3 3 Attempts to issue any of the protected instructions from User mode causes an exception event Table 3 2 Registers Accessible in User Mode Processor Registers Register Names Data Registers...

Page 133: ...rst a return address must be loaded into the RETI register Second an RTI must be issued Example Code to Enter User Mode Upon Reset Listing 3 1 provides code for entering User mode from the Reset state...

Page 134: ...he processor remains in User mode until one of these events occurs An interrupt NMI or exception event invokes Supervisor mode An emulation event invokes Emulation mode A reset event invokes the Reset...

Page 135: ...rces When RESET is deasserted the processor initiates operation by servicing the reset event Emulation is the only event that can preempt this activity Lower priority events cannot be processed One me...

Page 136: ...Table P0 H IVG15_EVT 16 0xFFFF P1 L START Point to start of User code P1 H START P0 P1 Place the address of start code in IVG15 of EVT P0 L IMASK 0xFFFF R0 W P0 R1 L IVG15 0xFFFF R0 R0 R1 W P0 R0 Set...

Page 137: ...has unrestricted access to all system resources Idle State Idle state stops all processor activity at the user s discretion usually to conserve power during lulls in activity No processing occurs dur...

Page 138: ...nable Register SIC_IWR on page 4 24 While not required an interrupt could also be enabled in conjunction with the WAKEUP signal When the WAKEUP signal is asserted the processor finishes executing the...

Page 139: ...ams in User mode cannot invoke the Reset state except through a system call provided by an operating system kernel Table 3 5 summarizes the state of the processor upon reset Table 3 5 Processor State...

Page 140: ...processor RESET pin causes a hardware reset Resets both the core and the peripherals including the Dynamic Power Manage ment Controller DPMC Resets the No Boot on Software Reset bit in SYSCR For more...

Page 141: ...watchdog timer appropriately causes a Watchdog Timer reset Resets both the core and the peripherals excluding the RTC block and most of the DPMC The DPMC resets only PLL_IOCK The Software Reset regis...

Page 142: ...ware or strapped high or low by resistor The sensed state is used to configure the phase locked loop For more information see Phase Locked Loop and Clock Control on page 8 2 System Reset Configuration...

Page 143: ...processor transitions into the boot mode sequence The boot mode is configured by the state of the BMODE and the No Boot on Software Reset control bits Figure 3 2 System Reset Configuration Register 0...

Page 144: ...when the register is read Bits 2 0 are read write When the BMODE pins are not set to b 000 and the No Boot on Software Reset bit in SYSCR is set the ADSP BF535 processor starts executing from the sta...

Page 145: ...reset period Booting Methods The internal boot ROM includes a small boot kernel that can either be bypassed or used to load user code from an external memory device as defined in Table 4 10 on page 4...

Page 146: ...to avoid initiating a download If this bit is set on a software reset the processor skips the normal boot sequence and jumps to the beginning of L2 memory and begins execution The boot kernel assumes...

Page 147: ...1 Nonsequential structures direct the ADSP BF535 processor to execute an instruction that is not at the next sequential address These structures include Loops One sequence of instructions executes sev...

Page 148: ...Sequencer are 32 bit memory instruction addresses Figure 4 1 Program Flow Variations N N 1 N 2 N 3 N 4 N 5 ADDRES S INS TRUCTION INS TRUCTION INS TRUCTION INS TRUCTION INS TRUCTION INS TRUCTION LINEAR...

Page 149: ...ndirect branches The Sequencer evaluates conditional instructions and loop termination conditions The loop registers support nested loops The memory mapped registers MMRs store information used to imp...

Page 150: ...sor mode Table 4 1 Sequencer Related Registers Register Name Description SEQSTAT Sequencer Status register Return Address registers See Events and Sequencing on page 4 17 RETX RETN RETI RETE RETS Exce...

Page 151: ...0 0 0 0 0 0 Sequencer Status Register SEQSTAT IDLE_REQ EXCAUSE 5 0 Holds information about the last executed exception See Table 4 11 This bit is set by the IDLE instruction 0 No pending request for i...

Page 152: ...ion Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 X X X X X X X X X X X X X 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X System Configuration Register SYSCFG...

Page 153: ...uction Pipeline Pipeline Stage Description Instruction Fetch 1 IF1 Start instruction memory access Instruction Fetch 2 IF2 Finish L1 instruction memory access and align instruction Instruction Decode...

Page 154: ...he cache every cycle For example for a series of 16 bit instructions the Alignment Unit gets data from the Instruction Memory Unit once in 4 cycles The alignment logic requests the next instruction ad...

Page 155: ...Interrupts and returns Loops Branches and Sequencing One type of nonsequential program flow that the Sequencer supports is branching A branch occurs when a JUMP or CALL instruction begins execu tion a...

Page 156: ...ot be delayed The Program Sequencer can evaluate the CC status bit to decide whether to execute a branch If no condition is specified the branch is always taken Conditional JUMP instructions use stati...

Page 157: ...instruction may be used If the destination requires more than a 13 bit offset then the JUMP L 0xnnnn instruction must be used If the destination offset is unknown and development tools must evaluate t...

Page 158: ...truction For example JUMP PC P3 CALL PC P0 Condition Code Flag The ADSP BF535 supports a condition code CC flag bit which is used to resolve the direction of a branch This flag may be accessed five wa...

Page 159: ...ual less than and less than or equal to There are also bit test operations that test whether a bit in a 32 bit register is set Conditional Branches The Sequencer supports conditional branches These ar...

Page 160: ...ual CC bit value to the predicted value If the value was mis predicted the branch is corrected and the correct address is available for the WB stage of the pipeline The branch latency for conditional...

Page 161: ...ated regis ters to support two nested loops The condition for terminating a loop is that the counter decreases to zero This condition tests whether the loop has completed the number of itera tions loa...

Page 162: ...0 LSETUP lp_start lp_end LCO P5 lp_start R5 R0 R1 ns R2 P2 R3 I1 lp_end R5 R5 R2 Two sets of loop registers are used to manage two nested loops LC 1 0 the Loop Count registers LT 1 0 the Loop Top addr...

Page 163: ...ch time in loops with more than four instructions by allowing fetches to take place while instructions in the loop buffer are being executed Events and Sequencing The Event Controller of the processor...

Page 164: ...sm The ADSP BF535 processor System Interrupt Controller SIC works with the Core Event Controller CEC to prioritize and control all system interrupts The SIC provides mapping between the many periph er...

Page 165: ...priority EMU Reset RST NMI NMI Exception EVX Reserved Hardware Error IVHW Core Timer IVTMR System Interrupts RTC USB PCI IVG7 SPORT0 RX TX SPORT1 RX TX IVG8 SPI0 SPI1 IVG9 UART0 RX TX UART1 RX TX IVG...

Page 166: ...ot masked the request proceeds to Step 4 4 The SIC_IARx registers which map the peripheral interrupts to a smaller set of general purpose core interrupts IVG7 IVG15 deter mine the core priority of Int...

Page 167: ...e not affected by the system level interrupt registers SIC_IWR SIC_ISR SIC_IMASK SIC_IARx If multiple interrupt sources share a single core interrupt then the ISR must identify the peripheral that gen...

Page 168: ...terrupt maps at reset The Core Interrupt ID used in the System Interrupt Assignment registers SIC_IARx See System Interrupt Assignment Registers SIC_IARx on page 4 29 Table 4 7 Peripheral Interrupt So...

Page 169: ...le then inter rupt initialization involves only initialization of the core EVT vector address entries and IMASK register and unmasking the specific peripheral interrupts in SIC_IMASK that the system r...

Page 170: ...Dynamic Power Management on page 8 1 By default all interrupts generate a wake up request to the core However for some applications it may be desirable to disable this function for some peripherals su...

Page 171: ...the interrupt usually by writing a system MMR to the time that the SIC senses that the interrupt has been deasserted Figure 4 6 System Interrupt Wakeup Enable Register 31 30 29 28 27 26 25 24 23 22 2...

Page 172: ...ocess all pending shared interrupts before executing the RTI which enables further interrupt generation on that interrupt input When an interrupt s service routine is finished the RTI instruction clea...

Page 173: ...stem Interrupt Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 System Interrupt St...

Page 174: ...Figure 4 8 System Interrupt Mask Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 System...

Page 175: ...equired for a particular system application For general purpose interrupts with multiple peripheral interrupts assigned to them take special care to ensure that software correctly processes all pendin...

Page 176: ...nterrupt IVG select SPI1 Interrupt IVG select 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 UART1 RX Interrupt IVG select UART1 TX Interrupt IVG select Timer 1 Interr...

Page 177: ...VT N event in the Event Vector Table The registers are IMASK interrupt mask ILAT interrupt latch IPEND interrupts pending The Event Controller updates ILAT and IPEND The IPEND register is read only in...

Page 178: ...ster ILAT Each bit in ILAT indicates when the corresponding event is latched see Figure 4 13 The bit is reset before the first instruction in the corre sponding ISR is executed Writes to any ILAT bit...

Page 179: ...used by the Event Controller to temporarily disable interrupts on entry and exit to an interrupt service routine When an event is processed the corresponding bit in IPEND is set The least significant...

Page 180: ...Blackfin Processor Programming Reference When program code is too time critical to be delayed by an interrupt dis able general purpose interrupts but be sure to re enable them at the conclusion of th...

Page 181: ...interrupt vectors are not determined by a fixed offset from an interrupt vector table base address This approach minimizes latency by not requiring a long jump from the vector table to the actual ISR...

Page 182: ...his location differs from that of other interrupts in that its content is read only Writes to this address have no effect The core has an output that indicates that a double fault has occurred This is...

Page 183: ...ut the ADSP BF535 processor boot ROM see Booting Methods on page 3 17 If the BMODE 2 0 pins indicate to bypass boot ROM the reset vector points to the start of the external asynchronous memory region...

Page 184: ...errupt If an exception occurs during handling of an NMI servicing the exception is delayed until completion of the NMI Exceptions Exception events are synchronous to the instruction that generates the...

Page 185: ...eserved before the excepting instruction For error conditions E the return address is the address of the instruction that caused the exception because some types of errors such as a page fault require...

Page 186: ...tion 0x21 E May be used to emulate instructions that are not defined for a particular processor implementation Illegal instruction combination 0x22 E See section for multi issue rules in the Blackfin...

Page 187: ...29 E Error from instruction fetch for example instruction bus parity error Instruction fetch mis aligned address viola tion 0x2A E Attempted misaligned instruction cache fetch On a misaligned instruc...

Page 188: ...an one CPLB entry matches instruction fetch address Illegal use of supervi sor resource 0x2E E Attempted to use a Supervisor register or instruction from User mode Supervisor resources are registers a...

Page 189: ...ated with an unrecoverable event code The address of the offending instruction is saved in RETX 8 Undefined Instruction 0x21 9 Illegal Combination 0x22 10 Illegal use protected resource 0x2E 11 DAG0 M...

Page 190: ...function Hardware errors occur when logic external to the core such as a memory bus controller is unable to complete a data transfer read or write and asserts the core s error input signal Such hardwa...

Page 191: ...dition HWERRCAUSE binary HWERRCAUSE hexadecimal Notes Examples DMA Bus Comparator Source 0b00001 0x01 The Compare Hit output is routed directly to the Hardware Error interrupt input The Com pare Hit i...

Page 192: ...for exceptions and emula tion EVX and EMU respectively It is recommended to reserve the two lowest priority interrupts IVG15 and IVG14 for software interrupt handlers Servicing Interrupts The CEC has...

Page 193: ...instructions after it are aborted 2 The return address is saved in the appropriate return register The return register is RETI for interrupts RETX for exceptions RETN for NMIs and RETE for debug emul...

Page 194: ...is already held in the RETI register Figure 4 15 shows an example of interrupt handling where interrupts are globally disabled for the entire interrupt service routine If nested interrupts are desire...

Page 195: ...LAT IPEND 0x0000 0x8000 Instruction I3 is RTI Clear IPEND 8 IPEND 4 jump to return address Instruction A1 is return address Interrupt is accept ed Bit ILAT 8 cleared and IPEND 8 set Return address pla...

Page 196: ...00 0x8110 ILAT IPEND 0x0000 0x8000 Instruction I3 is RTI Clear IPEND 8 IPEND 4 jump to return address Instruction A1 is return address Interrupt is accepted Bit ILAT 8 cleared and IPEND 8 set Return a...

Page 197: ...ves return address to stack SP ASTAT SP FP SP R7 0 P5 0 Body of service routine Note that none of the processor resources accumulators DAGs loop counters and bounds have been saved It s assumed that t...

Page 198: ...level sensitive interrupt requests from the peripherals The CEC provides edge sensitive detection for its general purpose inter rupts IVG7 IVG15 Consequently the SIC generates a synchronous interrupt...

Page 199: ...e routine executes an RTI On the other hand when self nesting interrupts are enabled an event interrupts processing at the same interrupt service level provided RETI is pushed to the stack and interru...

Page 200: ...contents of the RETI register when self nesting is enabled except for saving and restoring the register to the stack Exception Handling Interrupts and exceptions treat instructions in the pipeline di...

Page 201: ...the Force Interrupt Reset instruction RAISE When deferring the processing of an exception to lower priority interrupt IVGx the system must guarantee that IVGx is entered before returning to the applic...

Page 202: ...sing would typically be done here _EVENT1 RAISE 15 JUMP S _EXIT Entry for event at IVG14 _EVENT2 RAISE 14 JUMP S _EXIT comments for other events At the end of handler restore R0 P0 P1 and ASTAT and re...

Page 203: ...rn address on stack No change to ILAT or IPEND Put body of exception routine here RETX SP To return pop return address and jump No change to ILAT or IPEND RTX Return from exception Clear IPEND 3 Excep...

Page 204: ...r stack grows past a CPLB entry or SRAM block it may in fact generate an exception To guarantee that the Supervisor stack never generates an exception never overflows past a CPLB entry or SRAM block w...

Page 205: ...ne fill operation on the SBIU then when an interrupt occurs it is not held off until the fill has completed Instead the processor executes the ISR in its new context and the cache fill operation compl...

Page 206: ...execution before the load operation has completed then the ADSP BF535 processor continues to stall waiting for the fill to complete This same behavior is also exhibited for stalls involving reads of s...

Page 207: ...vides an address during a data move and auto increments decrements the stored address for the next move Supply address with offset provides an address from a base with an offset without incrementing t...

Page 208: ...pointed to by I0 into R0 Then modify the contents of I0 by the value contained in the M1 register Base and Length registers B 3 0 and L 3 0 32 bit Base and Length registers set up the range of address...

Page 209: ...ding L registers to zero for linear addressing or to the buffer length for circular buffer addressing All DAG registers must be initialized individually Initializing a B register does not automaticall...

Page 210: ...tion R0 P3 This instruction fetches a 32 bit word pointed to by the value in P3 and places it in R0 It then post increments P3 by four maintaining alignment with the 32 bit access R0 L W I3 This instr...

Page 211: ...ding on the current proces sor operating mode only one of these registers is active and accessible as SP In User mode any reference to SP for example stack pop R0 SP implicitly uses the USP as the eff...

Page 212: ...mory access Any M register can be used with any I register The modify value can also be an immediate value instead of an M register The size of the modify value must be less than or equal to the lengt...

Page 213: ...and 32 bit aligned respectively Circular buffering uses post modify addressing As seen in Figure 5 2 on the first post modify access to the buffer the DAG outputs the I register value on the address...

Page 214: ...Figure 5 2 Circular Data Buffers 0X0 0X1 0X2 0X3 0X4 0X5 0X6 0X7 0X8 0X9 0XA 1 2 3 0X0 0X1 0X2 0X3 0X4 0X5 0X6 0X7 0X8 0X9 0XA 4 5 6 0X0 0X1 0X2 0X3 0X4 0X5 0X6 0X7 0X8 0X9 0XA 7 8 9 0X0 0X1 0X2 0X3...

Page 215: ...ment instruction in Blackfin Processor Programming Reference Indexed Addressing With Index and Pointer Registers Indexed addressing uses the value in the Index or Pointer register as an effective addr...

Page 216: ...and an access of an 8 bit word updates the pointer by 1 Both 8 bit and 16 bit read operations may specify either to sign extend or zero extend the contents into the destination register Pointer regis...

Page 217: ...d as the effective address The value of the Pointer register is not updated For example P5 P1 0x10 is an acceptable offset but P5 P1 0x11 causes an alignment exception Be sure the offset is divisible...

Page 218: ...the pointer P5 For example R2 I2 M1 loads a 32 bit word into the destination register R2 It updates the value in the Index register I2 by the value in the Modify register M1 Modifying DAG and Pointer...

Page 219: ...Unless exceptions are dis abled violations of memory alignment cause an alignment exception Some instructions for example many of the Video ALU instructions automatically disable alignment exceptions...

Page 220: ...ent Auto decrement Indirect Indexed To and from Data Registers LOADS 32 bit word 16 bit zero extended half word 16 bit sign extended half word 8 bit zero extended byte 8 bit sign extended byte STORES...

Page 221: ...cates that the ADSP BF535 processor supports the addressing mode Table 5 2 Addressing Modes P Auto inc P Auto dec P Indirect P Indexed FP Indexed P Post inc I Auto inc I Auto dec I Indirect I Post inc...

Page 222: ...s of any Data Register File register Preg denotes any Pointer register FP or SP register Ireg denotes any DAG Index register Mreg denotes any DAG Modify register W denotes a 16 bit wide value B denote...

Page 223: ...y Instruction Preg Preg Preg Preg Preg Preg Preg Preg uimm6m4 Preg Preg uimm17m4 Preg Preg uimm17m4 Preg FP uimm7m4 Dreg Preg Dreg Preg Dreg Preg Dreg Preg uimm6m4 Dreg Preg uimm17m4 Dreg Preg uimm17m...

Page 224: ...g W Preg uimm16m2 X Dreg W Preg uimm16m2 X Dreg W Preg Preg X Dreg_hi W Ireg Dreg_hi W Ireg Dreg_hi W Ireg Dreg_hi W Preg Dreg_hi W Preg Preg Dreg_lo W Ireg Dreg_lo W Ireg Dreg_lo W Ireg Dreg_lo W Pre...

Page 225: ...reg Preg Preg uimm6m4 Preg Preg uimm17m4 Preg Preg uimm17m4 Preg FP uimm7m4 Preg Preg Dreg Preg Dreg Preg Dreg Preg uimm6m4 Dreg Preg uimm17m4 Dreg Preg uimm17m4 Dreg Preg Preg Dreg FP uimm7m4 Dreg Ir...

Page 226: ..._lo W Preg Dreg_lo W Preg Dreg W Preg Dreg W Preg Dreg W Preg uimm5m2 Dreg W Preg uimm16m2 Dreg W Preg uimm16m2 Dreg W Preg Preg Dreg_lo B Preg Dreg B Preg Dreg B Preg Dreg B Preg uimm15 Dreg B Preg u...

Page 227: ...a single cycle The L2 memories which include an on chip SRAM and off chip mapping to synchronous asynchronous and PCI devices provide much larger memory spaces with higher latencies The focus of this...

Page 228: ...ache line has been changed since it was copied from the source memory and therefore needs to be updated in that source memory exclusive clean The state of a data cache line indicating that the line is...

Page 229: ...latency to access little endian The native data store format of the ADSP 21535 processor Words and half words are stored in memory and registers with the least significant byte at the lowest byte addr...

Page 230: ...line that must be written to memory before it can be replaced to free space for a cache line allocation Way An array of line storage elements in an N Way cache see Figure 6 6 on page 6 18 write back...

Page 231: ...The ADSP BF535 processor also provides support for an external memory space that includes PCI space asynchronous memory space and synchro nous DRAM SDRAM space See PCI Bus Interface on page 13 1 and E...

Page 232: ...y Bank 0 16 MB 128 MB 0xEEFF FFFC 0xEEFF FF00 0xEEFE FFFF 0xEEFE 0000 0xE7FF FFFF 0xE000 0000 0x2FFF FFFF 0x2C00 0000 0x2800 0000 0x2400 0000 0x2000 0000 0x1800 0000 0x1000 0000 0x0800 0000 0x0000 000...

Page 233: ...e ADSP BF535 processor is reset see Booting Methods on page 3 17 Within the external memory map the PCI address range consists of PCI memory PCI I O space and PCI configuration space In addition four...

Page 234: ...DB 4K SRAM DCACHE SRAM ICACHE SRAM CONTROL PROCESSOR CORE D0 BUS CORE D1 BUS CORE I BUS 32 32 32 32 32 64 32 SYSL1 BUS SYSTEM BUS INTERFACE UNIT SBIU 32 KB BLOCK 0 SRAM MEMORY 32 KB BLOCK 7 SRAM MEMOR...

Page 235: ...simple programming model Caches eliminate the need to explicitly manage data movement into and out of the L1 memories Code can be ported to or developed for the ADSP BF535 processor quickly without re...

Page 236: ...f L1 Data SRAM The ADSP BF535 processor provides two 16 KB L1 data SRAM banks Data Bank A and Data Bank B Each 16 KB L1 data bank consists of four 4 KB sub banks This organization like the L1 Instruct...

Page 237: ...eed is critical For example the User and Supervisor stacks should be mapped to the scratch pad memory for the fastest context switching during interrupt handling The L1 memories operate at the core cl...

Page 238: ...DMEM_CONTROL The Data Memory Control register DMEM_CONTROL shown in Figure 6 3 contains control bits for the L1 Data Memory The reset values of the ENDM and DMC bits indicate that the L1 Instruction M...

Page 239: ...ine must enable CPLBs after adding entries for the exception and NMI service routines 00 Both data banks are SRAM 01 Reserved 10 Data Bank A is cache Data Bank B is SRAM 11 Both data banks are cache D...

Page 240: ...ister 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 X X X X X X X X X 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Instruction Memory Control Register IMEM_CON...

Page 241: ...pace generates an exception see Exceptions on page 4 38 Write access to the L1 instruction SRAM memory must be made through the 64 bit wide system DMA port Because the SRAM is implemented as four sing...

Page 242: ...sub banks Figure 6 5 describes the bank architecture of the L1 Instruction Memory Table 6 1 L1 Instruction Memory Sub Banks Memory Sub Bank Memory Start Location 0 0xFFA0 0000 1 0xFFA0 1000 2 0xFFA0 2...

Page 243: ...age 6 56 Figure 6 6 shows the overall Blackfin processor instruction cache organization Cache Lines As shown in Figure 6 6 the cache consists of a collection of cache lines Each cache line is made up...

Page 244: ...LINE 127 32 BYTE LINE 1 32 BYTE LINE 0 32 BYTE LINE 5 32 BYTE LINE 4 32 BYTE LINE 3 32 BYTE LINE 2 LINE 127 WAY2 VALID 1 20 TAG 32 BYTE LINE 5 32 BYTE LINE 4 32 BYTE LINE 3 LINE 127 32 BYTE LINE 0 WAY...

Page 245: ...nd Misses A cache hit occurs when the address for an instruction fetch request from the core matches a valid entry in the cache Specifically a cache hit is determined by comparing the upper 18 bits an...

Page 246: ...access to retrieve the missing cache line from memory that is exter nal to the core The address for the external memory access is the address of the target instruction word When a cache miss occurs th...

Page 247: ...line fill buffer organization is shown in Figure 6 8 During a line fill operation the line fill buffer s address tag contains the upper 18 bits plus bits 11 and 10 of the instruction fetch address Th...

Page 248: ...A page is considered non cacheable if the CPLB_L1_CHBL bit of the associ ated CPLB descriptor for the matching address is cleared Cache Line Replacement When the instruction memory unit is configured...

Page 249: ...y3 last For example If Way3 is invalid and Ways0 1 2 are valid Way3 is selected for the new cache line If Ways0 and 1 are invalid and Ways2 and 3 are valid Way0 is selected for the new cache line If W...

Page 250: ...instruction cache When the cache is enabled each sub bank of L1 Instruction Memory is a Way Setting the lock bit for a specific Way prevents state transitions for all the lines in that Way that is li...

Page 251: ...e cache line is simply invalidated In the following example the P2 register contains the address of a valid memory location If this address has been brought into cache the corre sponding cache line is...

Page 252: ...upper 32 bits are stored in the ITEST_DATA 1 register When the tag arrays are accessed ITEST_DATA 0 is used Graphic representations of the ITEST registers begin with Figure 6 9 on page 6 27 Before the...

Page 253: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X Instruction Test Command Register ITEST_COMMAND 00 Access sub bank 0 01...

Page 254: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22...

Page 255: ...TA0 Reset Undefined Valid 0 Cache line invalid 1 Cache line valid X Tag 19 4 Tag 3 2 Tag 1 0 Dirty 0 Cache line unmodified since it was copied from source memory 1 Cache line modified since it was cop...

Page 256: ...EM_CONTROL 16 R0 L 0X5 Enable instruction memory as cache R0 H 0X0 P0 R0 P1 L DMEM_CONTROL 0xFFFF P1 H DMEM_CONTROL 16 R0 L 0XD Enable data bank A and B as caches R0 H 0X0 P1 R0 csync Preloading the I...

Page 257: ...mmand for sub bank 0 m1 save command for sub bank 1 m2 save command for sub bank 2 m3 save command for sub bank 3 R7 L 0 R7 H 0 L0 R7 L1 R7 L2 R7 L3 R7 M0 R7 M1 R7 M2 R7 M3 R7 I0 L ITEST_COMMAND 0xFFF...

Page 258: ...set has 4 double words Routine Take way 0 and way 1 Inner loop Invalidate all sets cache lines in sub bank for way 0 and way 1 Instruction Cache has 32 sets cache lines hence loop count is 32 Outer lo...

Page 259: ...LBL3A lc1 p4 LBL0A r0 r4 r1 r5 lsetup LBL1A LBL2A lc0 p3 LBL1A r0 r0 r2 i0 r0 LBL2A r1 r1 r2 i0 r1 r4 r4 r3 LBL3A r5 r5 r3 R4 H 0x800 Initial value for ITEST_COMMAND for way 2 should be WRITE to TAG...

Page 260: ...idation routine is as follows Cache construction D CACHE 2 data banks each data bank has 4 sub banks each sub bank has 2 ways each way has 64 lines each line or set has 4 double words Routine Take way...

Page 261: ...counter Should be 2 for D cache P3 R2 Inner loop counter Number of set index Listing 6 3 Invalidating Bank A R4 H 0x00 Initial value for DTEST_COMMAND for way 0 should be WRITE to TAG R4 L 2 R5 H 0x4...

Page 262: ...0D LBL3D lc1 p4 LBL0D r0 r4 r1 r5 lsetup LBL1D LBL2D lc0 p3 LBL1D r0 r0 r2 i0 r0 LBL2D r1 r1 r2 i0 r1 r4 r4 r3 LBL3D r5 r5 r3 Configure L1 SRAM data banks as SRAM Default to DCBS 0 so LOWBIT bit14 sel...

Page 263: ...ure bits DMC 1 0 and the Enable Data Memory ENDM control bit in the DMEM_CONTROL register determines how the data banks are configured see Table 6 5 and Figure 6 3 on page 6 13 The ENDM bit is used to...

Page 264: ...ur Each of these regions is single ported and if address collision is detected access is granted first to system DMA then to the DAGs The division of each data bank into four sub banks allows code opt...

Page 265: ...L1 Data Memory architecture Table 6 6 L1 Data Memory SRAM Sub Bank Start Addresses Memory Sub Bank Data Bank A Data Bank B 0 0xFF80 0000 0xFF90 0000 1 0xFF80 1000 0xFF90 1000 2 0xFF80 2000 0xFF90 200...

Page 266: ...ve cache however L1 data cache has some unique fea tures that are described below The DCPLB descriptors control data cacheability Through these descrip tors the data cache can contain data from any ad...

Page 267: ...data banks are configured as cache the bank select mechanism is programmable The Data Cache Bank Select DCBS bit in the DMEM_CONTROL register selects either the large bank size or the small bank size...

Page 268: ...use Data Bank B In this case A 14 is treated as just another bit in the address that is stored with the tag in the cache and compared for Hit Miss pro cessing by the cache The result of choosing DCBS...

Page 269: ...KB 2 Way set associative cache In this instance the application never derives any benefit from Data Bank B For most applications it is best to operate with DCBS 0 When DCBS 1 on chip L2 memory is cac...

Page 270: ...each data cache as a multibank organization of subcaches Provided that the dual access DSP instructions address different subcaches and the cache line fill is not writing to the same bank address col...

Page 271: ...ted line space and the cache is configured for write back storage the controller checks the state of the cache line and treats it accordingly If the state of the line is exclusive clean the new tag an...

Page 272: ...access to fill the cache line is not cancelled and the data cache is updated with the new data before any further cache miss operations to the respective data bank are serviced For more information se...

Page 273: ...oes not exist FLUSH functions like a NOP FLUSHINV Data Cache Line Flush and Invalidate causes the data cache to perform the same function as the FLUSH instruction and then invalidate the specified lin...

Page 274: ...ed then DTEST_DATA 0 is used Before accessing the cache entries through the DTEST registers enable the L1 Data memories by setting the ENDM and DMC 1 0 bits and clearing the ENDCPLB bit in DMEM_CONTRO...

Page 275: ...ST_DATA1 shown in Figure 6 16 stores the upper 32 bits Figure 6 15 Data Test Command Register X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X...

Page 276: ...alid and Dirty bits which indicate the state of the cache line Figure 6 16 Data Test Data 1 Register X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X 15 14 13 12 11 10 9 8 7 6...

Page 277: ...X Tag 19 4 Tag 3 2 Tag 1 0 Dirty 0 Cache line unmodified since it was copied from source memory 1 Cache line modified after it was copied from source memory X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X...

Page 278: ...sor core is also supported The ADSP BF535 processor has a dedicated low latency 64 bit data path into the L2 SRAM memory At a core clock frequency of 300 MHz the peak data transfer rate across this in...

Page 279: ...with four 64 bit reads Under this condition the L1 cache line fills from the L2 SRAM in 7 1 1 1 10 cycles In other words after seven core cycles the first 64 bit 8 byte fill is available for the proc...

Page 280: ...ead is forwarded to the core as the line is filled Sequential memory accesses miss the cache only when they reach the end of a cache line When on chip L2 memory is configured as non cacheable instruct...

Page 281: ...tructions obtained from the previous fill Off Chip L2 Memory The external memory space is shown in Figure 20 1 on page 20 5 Four of the memory regions are dedicated to SDRAM support The size of each S...

Page 282: ...n interrupt from PCI or a DMA channel depending on where the access originated Because the PCI memory space is as large as the full memory address space of the ADSP BF535 processor a segmented or wind...

Page 283: ...are also divided between instruction and data CPLBs Sixteen CPLB entries are used for instruction fetch requests these are called ICPLBs Another sixteen CPLB entries are used for data transac tions th...

Page 284: ...re the same attributes such as access protection and cacheability therefore ideally only one descriptor for the entire range is needed In the case of the ADSP BF535 processor such a video frame buffer...

Page 285: ...cesses to this page use the L1 cache or bypass the cache If cacheable Write Through Write Back Data writes propagate directly to memory or are deferred until the cache line is reallocated Dirty Modifi...

Page 286: ...dress able space and never need to be replaced This type of definition is referred to as a static memory management model However operating environments commonly define more CPLB descrip tors to cover...

Page 287: ...into one of the on chip CPLB register pairs If all on chip registers contain valid CPLB entries the handler selects one of the descriptors to be replaced and the new descriptor information is loaded...

Page 288: ...n of memory spaces either between tasks or between User and Supervisor modes To protect memory between tasks the operating sys tem can maintain separate tables of instruction and or data memory pages...

Page 289: ...n MMU exception is generated to obtain a valid ICPLB descriptor to determine whether the memory is cacheable or not As a result if the L1 Instruction Memory is enabled as cache then any memory region...

Page 290: ...Async Non cacheable One 4 MB page Async Cacheable Two 4 MB pages MMRs Non cacheable 4 MB page L1 Data Non cacheable One 4 MB page Scratchpad Non cacheable 4 KB page SDRAM Cacheable Eight 4 MB pages As...

Page 291: ...service routine must set this bit 0 DCPLB entry not valid 1 DCPLB entry valid 0 DCPLB entry may be replaced 1 DCPLB entry may not be replaced 0 Read access not allowed in User mode If a read access is...

Page 292: ...0xFFE0 0200 DCPLB_DATA1 0xFFE0 0204 DCPLB_DATA2 0 xFFE0 0208 DCPLB_DATA3 0xFFE0 020C DCPLB_DATA4 0xFFE0 0210 DCPLB_DATA5 0xFFE0 0214 DCPLB_DATA6 0xFFE0 0218 DCPLB_DATA7 0xFFE0 021C DCPLB_DATA8 0xFFE0...

Page 293: ...1 4 KB page size 10 1 MB page size 11 4 MB page size PAGE_SIZE 1 0 Reset Undefined ICPLB_LOCK ICPLB_VALID ICPLB_L1_CHBL Clear this bit whenever L1 memory is configured as SRAM 0 Non cacheable in L1 1...

Page 294: ...0 0xFFE0 1200 ICPLB_DATA1 0xFFE0 1204 ICPLB_DATA2 0xFFE0 1208 ICPLB_DATA3 0xFFE0 120C ICPLB_DATA4 0xFFE0 1210 ICPLB_DATA5 0xFFE0 1214 ICPLB_DATA6 0xFFE0 1218 ICPLB_DATA7 0xFFE0 121C ICPLB_DATA8 0xFFE0...

Page 295: ...DCPLB Address Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X DCPLB Address Registers DCPLB_ADDRx Address for Match 21 6 Reset Undefined 31 30 29 28 27 26 25 24 23 22...

Page 296: ...DR0 0xFFE0 0100 DCPLB_ADDR1 0xFFE0 0104 DCPLB_ADDR2 0xFFE0 0108 DCPLB_ADDR3 0xFFE0 010C DCPLB_ADDR4 0xFFE0 0110 DCPLB_ADDR5 0xFFE0 0114 DCPLB_ADDR6 0xFFE0 0118 DCPLB_ADDR7 0xFFE0 011C DCPLB_ADDR8 0xFF...

Page 297: ...ICPLB Address Registers X X X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X ICPLB Address Registers ICPLB_ADDRx Address for Match 21 6 Reset Undefined 31 30 29 28 27 26 25 24 23 22...

Page 298: ...infer the cause of the fault by examining the CPLB entries Table 6 11 ICPLB Address Register MMR Assignments Register Name Memory Mapped Address ICPLB_ADDR0 0xFFE0 1100 ICPLB_ADDR1 0xFFE0 1104 ICPLB_A...

Page 299: ...17 16 X X X X X X X X X X X X X 0 X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCPLB Status Register DCPLB_STATUS 0 Access was read 1 Access was write FAULT_READWRITE Res...

Page 300: ...CPLB_FAULT_ADDR shown in Figure 6 29 hold the address that has caused a fault in the L1 Data Memory or L1 Instruction Memory respectively Figure 6 27 ICPLB Status Register X 31 30 29 28 27 26 25 24 23...

Page 301: ...re 6 28 DCPLB Fault Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X DCPLB Fault A...

Page 302: ...ss location addr B0 refers to the least significant byte of the 32 bit word Figure 6 29 ICPLB Fault Address Register Figure 6 30 Data Stored in Little Endian Order 31 30 29 28 27 26 25 24 23 22 21 20...

Page 303: ...nd addr 2 Load Store Operation The Blackfin processor architecture supports the RISC concept of a Load Store machine This machine is the characteristic in RISC architec tures whereby memory operations...

Page 304: ...sidered unimportant in the context of most memory operations Interlocked Pipeline In the execution of instructions the Blackfin processor architecture imple ments an interlocked pipeline When a load i...

Page 305: ...e updated values Store operations will eventually propagate to their ultimate destination Because of weak ordering the memory system is allowed to prioritize reads over writes In this case a write tha...

Page 306: ...sure that these effects do not occur in code that requires precise or strong ordering of load and store operations synchronization instructions CSYNC or SSYNC should be used Synchronizing Instructions...

Page 307: ...ories and the rest of the chip In addition to performing the core synchronization functions of CSYNC SSYNC flushes any write buffers between the L1 mem ory and the SBIU and generates a sync request to...

Page 308: ...whether the instruction should have executed Conditional Load Behavior The synchronization instructions force all speculative states to be resolved before a load instruction initiates a memory referen...

Page 309: ...ligned memory reference generates a Misaligned Access exception event see Exceptions on page 4 38 However because some data streams such as 8 bit video data can properly be unaligned in memory alignme...

Page 310: ...cesses even if the CPLB descriptor for the address indicates a cache enabled access If a cache hit is detected the line is flushed and invalidated before the TESTSET is allowed to proceed The ADSP BF5...

Page 311: ...read for reserved bits in a register Core MMR Programming Code Example Core MMRs may be accessed only as aligned 32 bit words Non aligned access to MMRs generates an exception event Listing 6 5 shows...

Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...

Page 313: ...ip interfaces and discusses the system interconnects including the System Bus Interface Unit SBIU and the associated system buses Internal Interfaces Figure 7 1 shows the core processor and system bou...

Page 314: ...of the Figure 7 1 ADSP BF535 Processor Bus Hierarchy PCI UART 1 PROG FLAG SPORT 1 SPI 1 BOOT ROM EBIU SPI 0 SPORT 0 UART 0 USB TIMERS RTC MEMORY DMA WATCHDOG TIMER EVENT BOOT CONTROLLER CLOCK AND POWE...

Page 315: ...ll bandwidth access from the pro cessor core The core includes the Level 1 L1 memory subsystem with 16 KB Instruction SRAM cache a dedicated 4 KB Scratchpad SRAM block and 32 KB of data SRAM cache con...

Page 316: ...e frequency have data paths up to 64 bits and sup port burst transfers All four ports have 32 bit address buses The Core D0 Figure 7 2 Blackfin Processor Core Block Diagram INT ACK TIMER EVENT CONTROL...

Page 317: ...e fill burst operations These requests are pipelined so that each transfer after the first is filled in a single consecutive cycle The Core I bus handles both instruction and data cache fills System O...

Page 318: ...unsupported interconnects Up to five parallel concurrent bus operations can be in progress in any one cycle For example A peripheral DMA channel is accessing L1 memory PCI is accessing L2 memory The c...

Page 319: ...ditional information about L2 memory see Memory on page 6 1 System Interfaces The ADSP BF535 processor system includes the peripheral set Timers Real Time Clock USB programmable flags UARTs SPORTs and...

Page 320: ...egion is not supported PAB Arbitration The core through the Core D0 bus and the PCI port through the EMB are the only masters on this bus A fixed priority arbitration policy is sup ported The PCI port...

Page 321: ...cessor core to access control and status state These registers are mapped into the system MMR space of the memory map System MMR addresses are listed in Appendix A Blackfin Proces sor Core MMR Assignm...

Page 322: ...ys tem Twelve DMA channels and bus masters support these devices The peripheral DMA controllers can transfer data between peripherals and one of Internal memory L1 or L2 memory through SBIU External m...

Page 323: ...edicated port into L1 memory The DAB and PCI share a port to L2 on chip memories No stalls occur as long as the core access PCI direct access and the DMA access are not to the same memory bank 4 KB si...

Page 324: ...L1 memory can only be stalled by An access already in progress from another DMA channel DMA read and write latency through the DAB to both on chip and off chip memory is shown in Table 7 3 The latenc...

Page 325: ...bus utilization is considerably higher due to the DAB s pipelined design Bus arbitration cycles are concurrent with the previous DMA access s data cycles Memory DMA transfers typically result in repea...

Page 326: ...ies in Table 7 2 A single arbiter supports a fixed priority arbitration policy for access to the DAB External Access Bus EAB The EAB provides a way for the processor core and the Memory DMA controller...

Page 327: ...used with the SBIU internal routing priorities shown in Table 7 1 EAB Performance The EAB supports single word accesses of either 8 bit 16 bit or 32 bit data types as well as 4 and 8 cycle bursts The...

Page 328: ...read 16 byte burst 48 12 120 44 4 PCI cycles for core delay and synchronization 1 PCI cycle for arbitration 1 PCI cycle for address 4 PCI cycles for data 2 PCI cycles for core delay and synchroni zat...

Page 329: ...each DMA or cache line read 32 byte burst access to 16 bit 100 ns flash 258 645 16 Worst case read latency DMA read 32 byte burst from SDRAM 13 4 318 10 page misses DMA read 16 byte burst from SDRAM 9...

Page 330: ...ternal memory space PCI mastered accesses to internal L2 memory have higher priority than core accesses to the same bank unless the core has the memory lock asserted or the core is in the middle of a...

Page 331: ...erarchy Resources Accessible From EMB The EMB provides access to L2 SRAM External memory System MMR space The EMB does not have access to L1 memory Boot ROM PCI space the PCI EAB slave cannot be acces...

Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...

Page 333: ...rnal clock multiplication by means of an on chip Phase Locked Loop PLL module In normal operation the user programs the PLL with a multipli cation factor for CLKIN The resulting multiplied signal is t...

Page 334: ...lexibility and control of power dissipation are key features This broad range of applica tions requires a wide range of frequencies for the clock generation circuitry The PLL interacts with the Dynami...

Page 335: ...lect MSEL 6 0 field configure the various PLL clock dividers The DF bit enables the input divider The MSEL 6 bit enables the output divider The MSEL 5 0 bits control the feedback dividers The feedback...

Page 336: ...L 5 is set to 1 DF must also be set to 1 Whether MSEL 5 and DF are set to 1 or both are set to 0 multiplica tion factors are the same See ADSP BF535 Blackfin Embedded Processor Data Sheet for maximum...

Page 337: ...4x 7x 7x 14x 14x 7x 14x 7x 14x 01111 15x 15x 15x 15x 10000 16x 16x 8x 8x 16x 16x 8x 16x 4x 8x 8x 16x 10001 17x 17x 17x 17x 10010 18x 18x 9x 9x 18x 18x 9x 18x 9x 18x 10011 19x 19x 19x 19x 10100 20x 20x...

Page 338: ...s ter should be modified with the new value This field can be changed at any time but changes to the divider ratio do not take effect until the PLL programming sequence is executed See PLL Programming...

Page 339: ...CTL register do not take effect immediately In general the PLL_CTL register is first programmed with new values and then a specific PLL programming sequence must be executed to implement the changes S...

Page 340: ...EL and DF fields can not be updated at the same time as the BYPASS field Should MSEL Figure 8 2 The PLL Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X 0 0 0 0 0 0 0 31 30 29...

Page 341: ...or core is idled that is an IDLE instruction has executed and the core awaits a wake up signal PLL_LOCKED This field is set to 1 when the internal PLL lock counter has incremented to the value set in...

Page 342: ...nd lock to the new frequencies The PLL Lock Count register PLL_LOCKCNT shown in Figure 8 4 defines the number of SCLK cycles that will occur before the processor sets the PLL_LOCKED bit in the PLL_STA...

Page 343: ...teristics and power dissipation profiles Peripheral clocks The user controls which peripherals are clocked and which are not saving power when a peripheral is idle or not used Voltage control The ADSP...

Page 344: ...annot be changed DMA access is available to both L1 and L2 memories From the Full On mode the processor can transition directly to the Active Sleep or Deep Sleep modes Active Mode In the Active mode t...

Page 345: ...however SCLK continues to run at the same frequency as before transitioning to the Sleep mode If the processor transitions from the Active mode to the Sleep mode SCLK con tinues to run at the Active...

Page 346: ...ore information about hardware reset see Hardware Reset on page 3 13 Note that an RTC interrupt in the Deep Sleep mode automatically resets some fields of the PLL Control register PLL_CTL as shown in...

Page 347: ...dicates that the STOPCK bit must be set to 1 and the PDWN bit must be set to 0 For information about how to effect mode transitions see Programming Operating Mode Transitions on page 8 17 Figure 8 5 O...

Page 348: ...et the PLL_OFF bit in the PLL_CTL register and then execute the PLL programming sequence PLL Enabled When the PLL is powered down power can be reap plied later when additional performance is required...

Page 349: ...zed only after executing a specific code sequence which is shown below This code sequence first brings the ADSP BF535 processor to a known idled state Once in this idled state the PLL recog nizes and...

Page 350: ...pply power to the PLL the PLL needs to relock To relock the PLL lock counter is first cleared then begins incrementing once per SCLK cycle After the PLL lock counter reaches the value programmed into...

Page 351: ...r immediately transitions to the Deep Sleep mode and waits for a Real Time Clock RTC interrupt or hardware reset signal An RTC interrupt causes the processor to enter the Active operating mode and con...

Page 352: ...zed and enabled as a wake up signal MSEL 6 0 and DF in PLL_CTL are set to b 0011111 and b 0 respectively signifying a CLKIN to CCLK multiplier of 31x Core clock CCLK to system clock SCLK divider ratio...

Page 353: ...r is now in the Active mode Listing 8 4 Changing CLKIN to CCLK Multiplier From 31x to 2x in Full On Mode R1 H 0x0000 set BYPASS bit in PLL_CTL without modifying MSEL because we must be in BYPASS to ch...

Page 354: ...or is now in the Full On mode with the CLKIN to CCLK multiplier set to 2x Peripheral Clocking To further reduce power dissipation the ADSP BF535 processor allows software to control the clocking of ma...

Page 355: ...can be accomplished when lower voltages are used The ADSP BF535 processor uses five power domains These power domains are shown in Table 8 6 Each power domain has a separate VDD supply Note the inter...

Page 356: ...by the application program See ADSP BF535 Blackfin Embedded Processor Data Sheet for more informa tion about voltage tolerances and allowed rates of change Reducing the ADSP BF535 processor s operatin...

Page 357: ...ernal Voltage Regulator Example A programmable voltage regulator external to the ADSP BF535 processor can be used to modify the operating voltage of the processor dynamically A simple handshaking mech...

Page 358: ...BF535 processor signals the voltage regulator via a programmable flag to lower the operating voltage then immedi ately executes the PLL programming sequence to begin the transition to the Active opera...

Page 359: ...is executed The ADSP BF535 processor signals the voltage regulator via a programmable flag to raise the operating voltage then immedi ately executes the PLL programming sequence to begin the transiti...

Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...

Page 361: ...es out the data transfers independent from processor activity The DMA controller can perform several types of data transfers Memory Memory MemDMA see Memory DMA Mem DMA on page 9 31 Memory Serial Peri...

Page 362: ...be found in DAB Perfor mance on page 7 11 DMA transfers on the ADSP BF535 processor can be descriptor based or autobuffer based Descriptor based DMA transfers require a set of param eters stored withi...

Page 363: ...set of parameters called a DMA descriptor block stored within memory Each descriptor block contains all the information needed for a particular DMA transfer sequence and consists of The 32 bit startin...

Page 364: ...of descriptor blocks is called a linked list see Figure 9 1 When a linked list has been generated the DMA channel has all the information needed to perform multiple transfer sequences without processo...

Page 365: ...as two 16 bit loads For this reason it is recommended DMA descriptor blocks be 32 bit aligned within memory At a minimum descriptor blocks must be 16 bit aligned Table 9 1 DMA Descriptor Block Parame...

Page 366: ...values for data size see Table 9 3 4 Autobuffer Peripheral dependent definition of values 5 6 Control State Peripheral dependent definition of values 7 Buffer Clear Must be set to 0 in Configuration W...

Page 367: ...endent data size can be 8 16 or 32 bits Some peripherals support only 16 and 32 bit data sizes With each trans fer the DMA address stored in the DMA Start Address registers increments relative to the...

Page 368: ...r for the current descriptor block including buffer status At the completion of the DMA transfer this information is written back to the DMA Configura tion Word of the current DMA descriptor block For...

Page 369: ...lock After the DMA transfer sequence bit 15 of the DMA Configuration Word is cleared returning own ership to the processor If ownership returns to the processor the DMA channel is still enabled but st...

Page 370: ...dy register see Peripheral DMA Descriptor Ready Register on page 9 25 This write triggers the DMA controller to recopy the DMA Con figuration Word from the current descriptor block into the DMA Config...

Page 371: ...k includes the final status of the transfer sequence Generates an interrupt if interrupts are enabled see the appropriate peripheral chapter for more information Fetches the Configuration Word of the...

Page 372: ...nel fetches remaining 4 elements from Descriptor Block A and performs DMA See Time T2 N NEXT PAGE Y N Did processor write to Descriptor Ready register occur DMA channel writes back contents of DMA Con...

Page 373: ...riptor Block Ownership bit bit 15 See Time T3 Y DMA channel fetches remaining 4 elements from Descriptor Block B and performs DMA See Time T4 N CONT D Y N Did processor write to Descriptor Ready regis...

Page 374: ...NFIGURATION WORD B TRANSFER COUNT B START ADDRESS 15 0 START ADDRESS 31 16 DMA_END DMA CONFIGURATION REGISTER DESCRIPTOR BLOCK B CONFIGURATION WORD B TRANSFER COUNT B START ADDRESS 15 0 START ADDRESS...

Page 375: ...ion points in the transfer sequence For more information about peripheral interrupts see the appropriate periph eral chapter Setting Up Autobuffer Based DMA The following steps illustrate the typical...

Page 376: ...ral DMA Configuration Register The peripheral s DMA Configuration register determines whether DMA is enabled and performs other essential DMA functions including func tions that are peripheral depende...

Page 377: ...tion Status RO 0 Processor 1 DMA engine DBO Descriptor Block Ownership RO 0 0 0 0 0 0 0 0 0 Read from memory 1 Write to memory Interrupt on Error Enable RO 0 Interrupt disabled 1 Interrupt enabled 0 D...

Page 378: ...ent descriptor block s Config uration Word in memory Then the next descriptor block s Configuration Word is loaded into the peripheral s DMA Configuration register If bit 15 of the Configuration Word...

Page 379: ...assignments for the peripheral DMA Transfer Count registers Figure 9 6 Peripheral DMA Transfer Count Register Table 9 5 Peripheral DMA Transfer Count Register MMR Assignments Register Name Memory Map...

Page 380: ...ndent of the transfer size 8 16 or 32 bits A DMA transfer sequence is complete when the transfer count reaches 0 UART0_COUNT_RX 0xFFC0 1A08 UART1_COUNT_RX 0xFFC0 1E08 UART0_COUNT_TX 0xFFC0 1B08 UART1_...

Page 381: ...heral DMA Start Address Register MMR Assignments Register Name Memory Mapped Address SPI0_START_ADDR_HI 0xFFC0 3204 SPI1_START_ADDR_HI 0xFFC0 3604 SPI0_START_ADDR_LO 0xFFC0 3206 SPI1_START_ADDR_LO 0xF...

Page 382: ...0xFFC0 2A04 SPORT1_START_ADDR_HI_RX 0xFFC0 2E04 UART0_START_ADDR_HI_RX 0xFFC0 1A04 UART1_START_ADDR_HI_RX 0xFFC0 1E04 UART0_START_ADDR_LO_RX 0xFFC0 1A06 UART1_START_ADDR_LO_RX 0xFFC0 1E06 USBD_DMABH H...

Page 383: ...eripheral s DMA Next Descriptor Pointer register deter mines the lower 16 bits of the descriptor block base address for the next DMA transfer sequence After initial configuration of the DMA register s...

Page 384: ...s not updated on DMA descriptor block fetches software controls it directly The DMA Descriptor Base Pointer must be restricted to L2 memory space This register is not used for autobuffer mode and is s...

Page 385: ...dy register remains set until a descriptor block has been successfully fetched After a successful fetch bit 0 of the DMA Descriptor Ready register is cleared Figure 9 10 describes the peripheral DMA D...

Page 386: ...alue from the peripheral s DMA Next Descriptor Pointer register before each DMA work block is fetched This register is not used for autobuffer mode Table 9 9 Peripheral DMA Descriptor Ready Register M...

Page 387: ...I1_CURR_PTR 0xFFC0 3600 SPORT0_CURR_PTR_RX 0xFFC0 2A00 SPORT1_CURR_PTR_RX 0xFFC0 2E00 SPORT0_CURR_PTR_TX 0xFFC0 2B00 SPORT1_CURR_PTR_TX 0xFFC0 2F00 UART0_CURR_PTR_RX 0xFFC0 1A00 UART1_CURR_PTR_RX 0xFF...

Page 388: ...0 360E SPORT0_IRQSTAT_RX 0xFFC0 2A0E SPORT1_IRQSTAT_RX 0xFFC0 2E0E SPORT0_IRQSTAT_TX 0xFFC0 2B0E SPORT1_IRQSTAT_RX 0xFFC0 2E0E UART0_IRQSTAT_RX 0xFFC0 1A0E UART1_IRQSTAT_RX 0xFFC0 1E0E UART0_IRQSTAT_T...

Page 389: ...or more information If the Interrupt on Completion IOC bit of the peripheral s DMA Con figuration register is set an interrupt is generated at the end of a DMA transfer sequence and the Completion IRQ...

Page 390: ...START_ ADDR_ HI SPIx_ START_ ADDR_ LO SPIx_ COUNT SPORTx RX SPORTx_ CONFIG_ DMA_ RX SPORTx_ NEXT_ DESCR_ RX SPORTx_ DESCR_ RDY_ RX SPORTx_ IRQSTAT_ RX SPORTx_ CURR_ PTR_RX SPORTx_ START_ ADDR_ HI_RX S...

Page 391: ...transfers use only part of the 32 bit data bus for each transfer therefore the throughput for these transfer sizes is less than for full 32 bit DMA operations The MemDMA controller does not support au...

Page 392: ...nts Because MemDMA provides only memory to memory DMA transfers MemDMA control registers contain no peripheral depen dent bits MemDMA control registers consist of source registers used to read from me...

Page 393: ...is read as a FIFO Status bit and written as a data size bit DMA Enable 0 Disabled 1 Enabled DBO Descriptor Block Owner RO Reset 0x0002 DCS DMA Completion Status RO 0 Successful completion 1 Error IOC...

Page 394: ...on Memory DMA Transfer Count regis ter The related DMA register is described in Peripheral DMA Transfer Count Register on page 9 19 Figure 9 14 Destination Memory DMA Transfer Count Register 15 14 13...

Page 395: ...s ters on page 9 21 Figure 9 15 Destination Memory DMA Start Address Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Destination Memory DMA Start Address High Register...

Page 396: ...dy reg ister The related DMA register is described in Peripheral DMA Descriptor Ready Register on page 9 25 Figure 9 16 Destination Memory DMA Next Descriptor Pointer Register Figure 9 17 Destination...

Page 397: ...criptor Pointer register The related DMA register is described in Peripheral DMA Current Descriptor Pointer Register on page 9 26 Figure 9 18 Destination Memory DMA Current Descriptor Pointer Register...

Page 398: ...heral DMA IRQ Status Regis ter on page 9 28 Figure 9 19 Destination Memory DMA Interrupt Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 Destination Memory DMA Interrupt...

Page 399: ...0 0 0 0 Reset 0x0000 DCS DMA Completion Status RO DMA Buffer Status 1 0 RO IOC Interrupt on Completion Enable RO Data Size Bit 0 RO 0 16 bit half word 1 8 bit byte or 32 bit word Data Buffer Clear 0...

Page 400: ...emory DMA Transfer Count register The related DMA register is described in Peripheral DMA Transfer Count Register on page 9 19 Figure 9 21 Source Memory DMA Transfer Count Register 15 14 13 12 11 10 9...

Page 401: ...t Address Registers on page 9 21 Figure 9 22 Source Memory DMA Start Address Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Source Memory DMA Start Address High Regist...

Page 402: ...register The related DMA register is described in Peripheral DMA Descriptor Ready Register on page 9 25 Figure 9 23 Source Memory DMA Next Descriptor Pointer Register Figure 9 24 Source Memory DMA Des...

Page 403: ...MA IRQ Status Regis ter on page 9 28 Figure 9 25 Source Memory DMA Current Descriptor Pointer Register Figure 9 26 Source Memory DMA Interrupt Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0...

Page 404: ...s highest throughput on block copies between external SDRAM and internal memory L1 to L2 transfer throughput is less because only the DAB bus is employed The Memory DMA controller performs a burst tra...

Page 405: ...ctive DMA processing This action causes loss of state and immediate termination of DMA processing The DMA channel does not relinquish the descriptor block back to the processor nor does it write back...

Page 406: ...ess the bus for data transfers The DMA Enable bit bit 0 of the Configuration Word is cleared A Bus Error interrupt is generated and Bit 2 of the IRQ Status reg ister is set The Configuration Word is n...

Page 407: ...wn set of control registers and data buffers With a range of configurable options the SPI ports provide a glueless hardware interface with other SPI compatible devices Typical SPI compatible periphera...

Page 408: ...ter environment by interfacing with several other devices acting as either a master device or a slave device In a multimaster environment the SPI interface uses open drain outputs to avoid data bus co...

Page 409: ...microcontrollers or microprocessors One mas ter device can also simultaneously shift data into multiple slaves known as broadcast mode However only one slave may drive its output to write data back t...

Page 410: ...control signal is driven by the master and controls the rate at which data is transferred The master may transmit data at a variety of baud rates SCK cycles once for each bit trans mitted It is an ou...

Page 411: ...directional I O data pins If the ADSP BF535 processor is configured as a master the MOSI pin becomes a data transmit output pin transmitting output data If the ADSP BF535 processor is configured as a...

Page 412: ...on of a DMA multiword transfer or upon an SPI error condition MODF TXE when TRAN 0 or RBSY when TRAN 1 When not using DMA mode an interrupt is generated when the SPI is ready to accept new data for a...

Page 413: ...See Error Signals and Flags on page 10 35 for more information about how the bits in these registers are used to signal errors and other condi tions See Register Functions on page 10 26 for more infor...

Page 414: ...word size Figure 10 3 SPIx Baud Rate Registers Table 10 1 SPIx Baud Rate Register MMR Assignments Register Name Memory Mapped Address SPI0_BAUD 0xFFC0 300A SPI1_BAUD 0xFFC0 340A Table 10 2 SPI Master...

Page 415: ...Send Zero Send 0 or last word when SPIx_TRBR empty 0 Send last word 1 Send 0s GM Get More Data When SPIx_RDBR full get data or discard incoming data 0 Discard incoming data 1 Get more data overwrite p...

Page 416: ...sabled 1 SPIxSEL1 enabled FLS2 Slave Select Enable 2 0 SPIxSEL2 disabled 1 SPIxSEL2 enabled FLS3 Slave Select Enable 3 0 SPIxSEL3 disabled 1 SPIxSEL3 enabled FLS4 Slave Select Enable 4 0 SPIxSEL4 disa...

Page 417: ...ponding PFx pin Slave Select Value FLGx bits When a PFx pin is configured as a slave select output the FLGx bits can determine the value driven onto the output If the CPHA bit in SPIx_CTL is set the o...

Page 418: ...ecause the SPI hardware automatically drives the PF3 pin Table 10 5 and Table 10 6 respectively list the SPI0_FLG and SPI1_FLG bit mapping to the PFx pins Table 10 5 SPI0_FLG Bit Mapping to PFx Pins B...

Page 419: ...s ignored The state of these input pins can be observed in the Flag Clear register FIO_FLAG_C or the Flag Set register FIO_FLAG_S Table 10 6 SPI1_FLG Bit Mapping to PFx Pins Bit Name Function PFx Pin...

Page 420: ...SPIx_FLG can be used in three cases In cases 1 and 2 the ADSP BF535 processor is the master and the seven microcontrollers peripherals with SPI interfaces are slaves The ADSP BF535 processor can Tran...

Page 421: ...its that just provide information about the SPI are read only These bits are set and cleared by the hardware Sticky bits are set when an error condi tion occurs These bits are set by hardware and must...

Page 422: ...ble 10 7 SPIx Status Register MMR Assignments Register Name Memory Mapped Address SPI0_ST 0xFFC0 3004 SPI1_ST 0xFFC0 3404 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x...

Page 423: ...beginning of a data transfer A write to SPIx_TDBR should not occur in this mode because this data will overwrite the DMA data to be transmitted When the DMA is enabled for receive operation the conte...

Page 424: ...are This register is at a different address than SPIx_RDBR but its contents are identical to that of SPIx_RDBR When a software read of SPIx_RDBR occurs the RXS bit in SPIx_ST is cleared and Table 10 8...

Page 425: ...memory In this mode many registers and con figuration bits are no longer writable since their values are loaded via descriptors These include the DMA Start Address and Count registers and DMA Configu...

Page 426: ...enating the Next Descriptor Base Pointer register DB_NDBP with the DMA Current Descriptor Pointer register Figure 10 11 SPIx DMA Current Descriptor Pointer Register Table 10 11 SPIx Current Descriptor...

Page 427: ...Data Size Bit 0 RO 0 16 bit half word 1 8 bit byte or 32 bit word Writable if DAUTO 1 DAUTO Autobuffer Descriptor Mode RW 0 Descriptor mode 1 Autobuffer mode FLSH DMA Buffer Clear RW Can be set follow...

Page 428: ...Name Memory Mapped Address SPI0_CONFIG 0xFFC0 3202 SPI1_CONFIG 0xFFC0 3602 Figure 10 13 SPIx DMA Start Address High and Low Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DMA Start Address 31 16 0...

Page 429: ...r Name Memory Mapped Address SPI0_START_ADDR_HI 0xFFC0 3204 SPI1_START_ADDR_HI 0xFFC0 3604 SPI0_START_ADDR_LO 0xFFC0 3206 SPI1_START_ADDR_LO 0xFFC0 3606 Figure 10 14 SPIx DMA Count Register Table 10 1...

Page 430: ...ss of the next descriptor block is the concatenation of two registers Next Descriptor Address 31 0 Next Descriptor Base Pointer 15 0 Next Descriptor Pointer 15 0 Figure 10 15 DMA Next Descriptor Point...

Page 431: ...WN 0 Write a 1 to bit 0 to reactivate a descriptor fetch Figure 10 16 SPIx DMA Descriptor Ready Register Table 10 16 SPIx DMA Descriptor Ready Register MMR Assignments Register Name Memory Mapped Addr...

Page 432: ...registers Figure 10 17 SPIx DMA Interrupt Register Table 10 17 SPIx DMA Interrupt Register MMR Assignments Register Name Memory Mapped Address SPI0_DMA_INT 0xFFC0 320E SPI1_DMA_INT 0xFFC0 360E 0 0 0 0...

Page 433: ...s as SPIx_RDBR but no action is taken when it is read SPIx_CURR_PTR SPI port DMA current pointer Register is always read only SPIx_CONFIG SPI port DMA con figuration Five of the control bits TRAN DCOM...

Page 434: ...ster master transmission The SCK signal is generated by the master and the SPISS signal is the slave device select input to the slave from the master The dia grams represent an 8 bit transfer SIZE 0 w...

Page 435: ...ain active low between successive transfers or be inactive high This must be controlled by the software by manipulating SPIx_FLG Figure 10 18 shows the SPI transfer protocol for CPHA 0 Note that SCK s...

Page 436: ...SPI transmission and reception are always enabled simultaneously unless the broadcast mode has been selected In broadcast mode several slaves can be enabled to receive but only one of the slaves must...

Page 437: ...on both the MOSI and MISO pins when this option is selected The WOM bit controls this feature When WOM is set and the ADSP BF535 SPI is configured as a master the MOSI pin is three stated when the dat...

Page 438: ...nd SPIx_BAUD registers enabling the device as a master and configuring the SPI system by specifying the appropriate word length transfer format baud rate and other necessary information If CPHA 1 the...

Page 439: ...ve buffer is full the incoming data is discarded and SPIx_RDBR is not updated Transfer Initiation From Master Transfer Modes When a device is enabled as a master the initiation of a transfer is define...

Page 440: ...e SPISS falling edge is detected the slave starts sending and receiving data on active SCK edges Reception transmission continues until SPISS is released or until the slave has received the proper num...

Page 441: ...is full the incoming data is discarded and SPIx_RDBR is not updated Slave Ready for a Transfer Table 10 20 shows the actions necessary to prepare the device for a new transfer when a device is enabled...

Page 442: ...Until the MODF bit is cleared the SPI cannot be re enabled even as a slave Hardware prevents the user from setting either SPE or MSTR while MODF is set When MODF is cleared the interrupt is deactivate...

Page 443: ...he SZ bit in SPIx_CTL The TXE bit is sticky W1C Reception Error RBSY The RBSY flag is set in SPIx_ST when a new transfer is completed before the previous data can be read from SPIx_RDBR The state of t...

Page 444: ...nes when the receive buffer can be read The TXS bit defines when the transmit buffer can be filled The end of a single word transfer occurs when the RXS bit is set indicating that a new word has just...

Page 445: ...ence 10 39 SPI Compatible Port Controllers into SPIx_RDBR because of the latency Therefore for SPIx_BAUD 2 or SPIx_BAUD 3 RXS must be set before SPIF to read SPIx_RDBR For larger SPIx_BAUD settings RX...

Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...

Page 447: ...de synchronous serial data transfer only the ADSP BF535 processor provides asynchro nous RS 232 data transfer via the UARTs Each SPORT is a full duplex device capable of simultaneous data transfer in...

Page 448: ...core or received from an external source The SPORTs can operate with little endian or big endian transmission formats with word lengths selectable from 3 to 16 bits They offer selectable transmit mod...

Page 449: ...for multiple data blocks Has a multichannel mode for TDM interfaces Each SPORT can receive and transmit data selectively from channels of a time divi sion multiplexed serial bitstream multiplexed int...

Page 450: ...signal The framing signal can occur either at the begin ning of an individual word or at the beginning of a block of words Figure 11 1 shows a simplified block diagram of a single SPORT Data to be tr...

Page 451: ...cc ess T X D M A M aster R X n R ec eiv e D a ta R eg ister T X n T ra n sm it D ata R eg ister T ran sm it S h ift R eg ister R ece iv e S h ift R eg ister S erial C o n tro l In te rn al S C L K G...

Page 452: ...SPORT s SPORTx_TX register readies the SPORT for trans mission The TFS signal initiates the transmission of serial data Once transmission has begun each value written to the SPORTx_TX register is tra...

Page 453: ...PORTx_TX_CONFIG control register and RSPEN in the SPORTx_RX_CONFIG control register respectively Each method has a different effect on the SPORT A reset disables the SPORTs by clearing the SPORTx_TX_C...

Page 454: ...the SPORT by clearing TSPEN in SPORTx_TX_CONFIG and or RSPEN in SPORTx_RX_CONFIG Each SPORT has its own set of control registers and data buffers These registers are described in detail in the followi...

Page 455: ..._TSCLKDIV and multichannel mode channel enable registers Writes are always enabled to the SPORTx_TX buffer SPORTx_RX is a read only register After a write to a SPORT register any changes to the contro...

Page 456: ...Internal Transmit Clock Select DTYPE 1 0 Data Formatting Type Select SENDN Endian Format Select TSPEN Transmit Enable LTFS Low Transmit Frame Sync Select LATFS Late Transmit Frame Sync 0 Early frame s...

Page 457: ...ce TX interrupts before setting TSPEN Clearing TSPEN causes the SPORT to stop driving data and frame sync pins it also shuts down the internal SPORT circuitry In low power applications battery life ca...

Page 458: ...e 15 to transmit a full 16 bit word and 7 to transmit an 8 bit byte The ADSP BF535 processor is a 16 bit processor so program instruction or DMA engine loads of the TX data register always move 16 bit...

Page 459: ...ular frame sync pulses DITFS should be set and the core should keep loading the SPORTx_TX register on time If the receiver can tolerate occasional late frame sync pulses DITFS should be cleared to pre...

Page 460: ...ck Select DTYPE 1 0 Data Format ting Type Select SENDN Endian Format Select RSPEN Receive Enable LRFS Low Receive Frame Sync Select LARFS Late Receive Frame Sync 0 Early frame syncs 1 Late frame syncs...

Page 461: ...o rewrite SPORTx_RX_CONFIG with all of the necessary bits including RSPEN Setting RSPEN enables the SPORT RX interrupt For this reason the code should initialize the interrupt service routine and be r...

Page 462: ...can be set to a value of 2 to 15 0 and 1 are illegal values for this field Internal Receive Frame Sync Select SPORTx_RX_CONFIG 9 IRFS This bit selects whether the SPORT uses an internal RFS if set or...

Page 463: ...1 1 on page 11 5 Two 16 bit words may be stored in these registers at any one time When the SPORTx_TX register is loaded and any previous word has been transmitted the contents are automatically loade...

Page 464: ...the core processor to attempt a write to a full SPORTx_TX register the new data overwrites the SPORTx_TX register If it is not known whether the core processor can access the SPORTx_TX register withou...

Page 465: ...cond if the first word has not been read out by the Master core or the DMA controller When this happens the receive overflow status bit ROVF is set in the SPORT Status register The overflow status is...

Page 466: ...e system clock frequency as determined by SSEL MSEL and DF and the value of the 16 bit serial clock divide modulus registers SPORTx_TSCLKDIV and SPORTx_RSCLKDIV These registers are shown in Figure 11...

Page 467: ...Tx Receive Serial Clock Divider Register MMR Assignments Register Name Memory Mapped Address SPORT0_RSCLKDIV 0xFFC0 280A SPORT1_RSCLKDIV 0xFFC0 2C0A SPORTx Transmit Serial Clock Divider Register SPORT...

Page 468: ...ther internally or externally generated serial clocks The SPORTx_TFDIV register is shown in Figure 11 9 the SPORTx_RFSDIV register is shown in Figure 11 10 Figure 11 9 SPORTx Transmit Frame Sync Divid...

Page 469: ...ansmit underflow status bit TUVF is set in the SPORT Status regis ter when a transmit frame sync occurs and no new data has been loaded into the SPORTx_TX register The TUVF status bit is sticky and is...

Page 470: ...value is reset to 0 after the offset has been com pleted For example with offset equal to 21 and a window of 8 in the regular mode the counter displays a value between 0 and 28 while in Channel Selec...

Page 471: ...ls The SPORTx_MTCSx register shown in Figure 11 12 specifies the active transmit channels Each register has 16 bits corre sponding to the 16 channels Setting a bit enables that channel so that the ser...

Page 472: ...TCS0 0xFFC0 2812 SPORT1_MTCS0 0xFFC0 2C12 SPORT0_MTCS1 0xFFC0 2814 SPORT1_MTCS1 0xFFC0 2C14 SPORT0_MTCS2 0xFFC0 2816 SPORT1_MTCS2 0xFFC0 2C16 SPORT0_MTCS3 0xFFC0 2818 SPORT1_MTCS3 0xFFC0 2C18 SPORT0_M...

Page 473: ...16 bits correspond ing to the 16 channels Setting a bit enables that channel so that the serial port selects that word for receive from the multiple word block of data For example setting bit 0 selec...

Page 474: ...ORT0_MRCS3 0xFFC0 2828 SPORT1_MRCS3 0xFFC0 2C28 SPORT0_MRCS4 0xFFC0 282A SPORT1_MRCS4 0xFFC0 2C2A SPORT0_MRCS5 0xFFC0 282C SPORT1_MRCS5 0xFFC0 2C2C SPORT0_MRCS6 0xFFC0 282E SPORT1_MRCS6 0xFFC0 2C2E SP...

Page 475: ...A value of zero for MFD causes the frame sync to be concurrent with the first data bit The maximum value allowed for MFD is 15 A new frame sync may occur before data from the last frame has been recei...

Page 476: ...xFFC0 2C34 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPORTx Multichannel Configuration 2 Registers SPORTx_MCMC2 0x Bypass mode 10 Recover 2 MHz clock from 4 MHz 11 Recover...

Page 477: ...ation SPORTx_CONFIG_DMA_RX Registers During SPORT initialization the program can write the head address of the first DMA descriptor block to the Receive DMA Next Descriptor Pointer register and then s...

Page 478: ...DMA writes to memory smaller than the 16 bit FIFO size only the LSBs of the FIFO are written A DMA read of memory greater than the 16 bit FIFO size reads only the LSBs of memory into the FIFO For DMA...

Page 479: ...ble if DAUTO 1 0 Processor 1 DMA engine 0 No error detected 1 Error detected ROVF FS 1 0 DMA Buffer Status RO 00 Buffer empty 01 One word present 10 Two words present 11 Three words present DCOME Inte...

Page 480: ...Tx_START_ADDR_LO_RX form the 32 bit address for data access Figure 11 18 SPORTx Receive DMA Start Address High Registers Table 11 17 SPORTx Receive DMA Start Address High Register MMR Assignments Regi...

Page 481: ...DDR_HI_RX and SPORTx_START_ADDR_LO_RX form the 32 bit address for data access Figure 11 19 SPORTx Receive DMA Start Address Low Registers Table 11 18 SPORTx Receive DMA Start Address Low Register MMR...

Page 482: ...RX and the DB_NDBP registers form the 32 bit head address of the next descriptor block During SPORT initialization the programmer writes the head address of the first DMA descriptor block to the Recei...

Page 483: ...Descriptor Ready SPORTx_DESCR_RDY_RX Registers The DMA engine stalls if a low level ownership bit is detected during a descriptor block access Writing a 1 to bit 0 of the SPORT Receive DMA Descriptor...

Page 484: ...CONFIG_DMA_RX configuration register The third source bus error is not maskable at the DMA level All three interrupt status bits contained within the SPORTx_IRQSTAT_RX register are sticky Figure 11 22...

Page 485: ...tus Registers Table 11 22 SPORTx Receive DMA IRQ Status Register MMR Assignments Register Name Memory Mapped Address SPORT0_IRQSTAT_RX 0xFFC0 2A0E SPORT1_IRQSTAT_RX 0xFFC0 2E0E 15 14 13 12 11 10 9 8 7...

Page 486: ...DMA_TX Registers During SPORT initialization the program can write the head address of the first DMA descriptor block to the Transmit DMA Next Descriptor Pointer register shown in Figure 11 29 on page...

Page 487: ...r 32 bits This provides flexibility in how data is packed in memory For DMA writes to memory in excess of the 16 bit FIFO size the upper bits are padded with zeros For DMA writes to memory smaller tha...

Page 488: ...rship RO 0 Memory read 1 Memory write Set to 0 for transmit DMA master Writable if DAUTO 1 0 Processor 1 DMA engine 0 No error detected 1 Error detected TUVF FS 1 0 DMA Buffer Status RO 00 Buffer empt...

Page 489: ...smit DMA Configuration Register MMR Assignments Register Name Memory Mapped Address SPORT0_CONFIG_DMA_TX 0xFFC0 2B02 SPORT1_CONFIG_DMA_TX 0xFFC0 2F02 Figure 11 26 SPORTx Transmit DMA Start Address Hig...

Page 490: ...I_TX and SPORTx_START_ADDR_LO_TX form the 32 bit address for data access Figure 11 27 SPORTx Transmit DMA Start Address Low Registers Table 11 26 SPORTx Transmit DMA Start Address Low Register MMR Ass...

Page 491: ..._TX and the DB_NDBP registers form the 32 bit head address of the next descriptor block During SPORT initialization the programmer writes the head address of the first DMA descriptor block to the Tran...

Page 492: ...riptor Ready SPORTx_DESCR_RDY_TX Registers The DMA engine stalls if a low level ownership bit is detected during a descriptor block access Writing a 1 to bit 0 of the SPORT Transmit DMA Descriptor Rea...

Page 493: ...configuration register The third source bus error is not maskable at the DMA level All three interrupt status bits contained within the SPORTx_IRQSTAT_TX register are sticky Figure 11 30 SPORTx Transm...

Page 494: ...hich they occurred and the register reads back the newly written value on the next cycle after that Figure 11 31 SPORTx Transmit DMA IRQ Status Registers Table 11 30 SPORTx Transmit DMA IRQ Status Reg...

Page 495: ..._SCLK1 pin and the value of the 16 bit serial clock divide modulus registers SPORTx_TSCLKDIV and SPORTx_RSCLKDIV SPxTCLK frequency SCLK frequency 2 SPORTx_TSCLDIV 1 SPxRCLK frequency SCLK frequency 2...

Page 496: ...sor can be used as a counter for dividing an external clock or for generating a periodic pulse or periodic interrupt The SPORT must be enabled for this mode of operation to work Maximum Clock Rate Res...

Page 497: ...G and SPORTx_RX_CONFIG registers of each SPORT determines the word length according to this formula Serial Word Length SLEN 1 The SLEN value should not be set to zero or one values from 2 to 15 are al...

Page 498: ...icant bits are transmitted Companding Companding a contraction of COMpressing and exPANDing is the pro cess of logarithmically encoding and decoding data to minimize the number of bits that must be se...

Page 499: ...Tx_TX_CONFIG and SPORTx_RX_CONFIG registers Serial clock frequency is configured in the SPORTx_TSCLKDIV and SPORTx_RSCLKDIV registers The receive clock pin may be tied to the transmit clock if a singl...

Page 500: ...ed control bits determine whether frame sync signals are required These bits are located in the SPORTx_TX_CONFIG and SPORTx_RX_CONFIG registers When TFSR 1 or RFSR 1 a frame sync signal is required fo...

Page 501: ...s reception Active low or active high frame syncs are selected with the LTFS and LRFS bits of the SPORTx_TX_CONFIG and SPORTx_RX_CONFIG registers See Timing Examples on page 11 69 for more timing exam...

Page 502: ...nerated internally or externally Active Low Versus Active High Frame Syncs Frame sync signals may be either active high or active low in other words inverted The LTFS and LRFS bits of the SPORTx_TX_CO...

Page 503: ...LKx to be used to drive internally generated frame syncs and selects the falling edge of RCLKx to be used to sample data and externally gener ated frame syncs Note externally generated data and frame...

Page 504: ...n LATFS 1 or LARFS 1 late frame syncs are configured this is the alternate mode of operation In this mode the first bit of the transmit data word is available and the first bit of the receive data wor...

Page 505: ...inuous generation of the TFS signal with or without new data The DITFS bit of the SPORTx_TX_CONFIG register configures this option When DITFS 0 the internally generated TFS is only output when a new d...

Page 506: ...channel mode of operation which allows the SPORT to communicate in a time division multiplexed TDM serial sys tem In multichannel communications each data word of the serial bit stream occupies a sepa...

Page 507: ...RT Multichannel Receive Select register must be programmed before enabling SPORTx_TX SPORTx_RX operation This is especially important in DMA data unpacked mode since SPORT FIFO operation begins immedi...

Page 508: ...frame sync This is true whether RFS is gener ated internally or externally The RFS signal is used to synchronize the channels and restart each multichannel sequence Assertion of RFS occurs at the begi...

Page 509: ...has started all other FS signals are ignored by the SPORT until the complete frame has been transferred In multichannel mode the RFS signal is used for the block or frame start reference after which...

Page 510: ...e start of the window A value of 0 specifies no offset and permits using all 128 channels As an example a program could define a window with a window size of 5 and an offset of 93 This 5 channel windo...

Page 511: ...sets to 0 after counting up to 21 and the frame completes when the CHNL reaches a value of 7 indicating the eighth channel The FSDR bit in the SPORTx_MCMC2 register changes the timing relationship bet...

Page 512: ...the word in that channel s position of the data stream Clearing the bit in the SPORTx_MTCSx register causes the SPORT s DT data transmit pin to three state during the time slot of that channel Setting...

Page 513: ...led channels the SPORT expects the DMA buffer to contain 10 consecutive words for each of the frames It is not possible to change the total number of enabled channels without changing the DMA buffer s...

Page 514: ...mitting an entire block or multiple blocks of serial data before the interrupt is generated The SPORT s DMA controller handles the DMA transfer allowing the pro cessor core to continue running until t...

Page 515: ...ock mode which includes a non divide bypass mode for nor mal operation SPORT Pin Line Terminations The ADSP BF535 processor has very fast drivers on all output pins including the SPORTs If connections...

Page 516: ...ow the input timing requirement for an externally generated frame sync and also the output timing characteristic of an internally generated frame sync Note the output meets the input timing requiremen...

Page 517: ...ng respectively in the unframed mode A sin gle frame sync signal occurs only at the start of the first word either one SCK before the first bit in normal mode or at the same time as the first bit in a...

Page 518: ...Figure 11 39 SPORT Receive Unframed Mode Normal Framing SCK OUTPUT RFS DR RFS INPUT B3 B2 B1 B0 B3 B2 B1 B0 SPORT Control Register Both Internal Framing Option and External Framing Option Shown SCK OU...

Page 519: ...g Figure 11 42 SPORT Continuous Transmit Normal Framing SCK RFS DR B3 B2 B1 B0 B3 B2 B1 B0 B2 B3 B2 B1 B0 SCK OUTPUT TFS DT TFS INPUT B3 B2 B1 B0 B3 SPORT Control Register Both Internal Framing Option...

Page 520: ...PORT Control Register Both Internal Framing Option and External Framing Option Shown Note There is an asynchronous delay between TFS input and DT See the appropriate datasheet for specifications SCK O...

Page 521: ...nce 11 75 Serial Port Controllers Figure 11 46 SPORT Transmit Unframed Mode Alternate Framing SCK TFS DT B3 B3 B0 B1 B2 B1 B0 B3 B2 B2 Note There is an asynchronous delay between TFS input and DT See...

Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...

Page 523: ...ART1 UART0 enhances the standard functionality and supports the half duplex IrDA SIR 9 6 115 2 Kbps rate protocol Modem status and control registers are available but only the transmit TX and receive...

Page 524: ...t With the optional parity bit this creates a 7 to 12 bit range for each word Data is always transmitted and received least significant bit LSB first Figure 12 1 shows a typical physical bit stream me...

Page 525: ...mes Figure 12 2 shows the bits in this register Figure 12 2 UARTx Line Control Registers 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Reset 0x00 0 0 DLAB Divisor Latch Access 1 Enables access to UARTx_DLL and UARTx_DL...

Page 526: ...Register Name Memory Mapped Address UART0_LSR 0xFFC0 180A UART1_LSR 0xFFC0 1C0A 0 DR Data Ready 7 6 5 4 3 2 1 0 0 1 1 0 Reset 0x60 0 0 TEMT TSR and UARTx_THR Empty 0 UARTx Line Status Registers UARTx...

Page 527: ...where it is shifted out at a baud rate equal to SCLK 16 Divisor with start stop and parity bits appended as required All data words begin with a 1 to 0 transition start bit The transfer of data from U...

Page 528: ...eady DR status flag is updated A sampling clock equal to 16 times the baud rate samples the data as close to the midpoint of the bit as possible Because the internal sample clock may not exactly match...

Page 529: ...individually by the control bits in this register An Interrupt Service Routine ISR evaluates the UARTx_IIR register to deter mine the signaling interrupt source The UARTx_IER register is mapped to th...

Page 530: ...ignments Register Name Memory Mapped Address UART0_IER 0xFFC0 1802 UART1_IER 0xFFC0 1C02 0 0 0 0 ERBFI Enable Receive Buffer Full Interrupt 7 6 5 4 3 2 1 0 0 0 Reset 0x00 0 0 UARTx Interrupt Enable Re...

Page 531: ...535 processor the Modem Status interrupt is not gener ated if the LOOP bit in the UARTx Modem Control register UARTx_MCR is not set UARTx Interrupt Identification Registers UARTx_IIR In non DMA mode a...

Page 532: ...These registers form a 16 bit divisor The baud clock is divided by 16 so that BAUD RATE SCLK 16 Divisor Divisor 65 536 when UARTx_DLL UARTx_DLH 0 Figure 12 7 UARTx Interrupt Identification Registers...

Page 533: ...r Latch High Byte Registers Table 12 7 UARTx Divisor Latch Low Byte Register MMR Assignments Register Name Memory Mapped Address UART0_DLL 0xFFC0 1800 UART1_DLL 0xFFC0 1C00 Table 12 8 UARTx Divisor La...

Page 534: ...s UARTx Modem Control Registers UARTx_MCR The UARTx_MCR register contains modem control and test signals as shown in Figure 12 9 Loopback mode forces the TX pin to high and disconnects the RX pin from...

Page 535: ...that enables com patibility with PC standard UART devices Figure 12 9 UARTx Modem Control Registers Table 12 10 UARTx Modem Control Register MMR Assignments Register Name Memory Mapped Address UART0_...

Page 536: ...since UARTx_MSR last read 1 CTS changed state since UARTx_MSR last read DDSR Delta DSR 0 DSR has not changed state since UARTx_MSR last read 1 DSR changed state since UARTx_MSR last read TERI Trailing...

Page 537: ...ta is moved to and from the UART by the proces sor core To transmit a character load it into UARTx_THR Received Data can be read from UARTx_RBR The ADSP BF535 processor must write and read one charact...

Page 538: ...to move Note that because polling is processor inten sive it is not typically used in real time signal processing environments Alternatively UART writes and reads can be accomplished by ISRs Both UAR...

Page 539: ...ers The TX DMA has its own dedicated inter rupt channel The receive interrupt channel handles RX DMAs as well as receive error conditions when enabled in the UARTx Receive DMA Con figuration register...

Page 540: ...egisters Each of the two UART modules provides two complete independent DMA channels The transmit channel reads from memory and the receive channel writes to memory Every DMA channel features its own...

Page 541: ...r Base Pointer Register DMA_DBP For more information on the DMA Descriptor Base Pointer Register see Direct Memory Access on page 9 1 Figure 12 12 UARTx Receive DMA Current Descriptor Pointer Register...

Page 542: ...rrupt on Completion RO Data Size Bit 0 RO Autobuffer 0 No error detected 1 Error detected 00 Buffer empty 11 Buffer full Actively updated in register 0 16 bit half word or 32 bit word 1 8 bit byte Thi...

Page 543: ...Tx_IRQSTAT_RX register in order to determine whether it was requested by a line error condition rather than by the DMA completion If this bit is set the service routine should read the UARTx_LSR regis...

Page 544: ...sters UARTx_START_ADDR_HI_RX Figure 12 14 shows the UARTx Receive DMA Start Address High registers Figure 12 14 UARTx Receive DMA Start Address High Registers Table 12 16 UARTx Receive DMA Start Addre...

Page 545: ...Low Registers Table 12 17 UARTx Receive DMA Start Address Low Register MMR Assignments Register Name Memory Mapped Address UART0_START_ADDR_LO_RX 0xFFC0 1A06 UART1_START_ADDR_LO_RX 0xFFC0 1E06 15 14 1...

Page 546: ...MA Count Registers Table 12 18 UARTx Receive DMA Count Register MMR Assignments Register Name Memory Mapped Address UART0_COUNT_RX 0xFFC0 1A08 UART1_COUNT_RX 0xFFC0 1E08 15 14 13 12 11 10 9 8 7 6 5 4...

Page 547: ...tor Base Pointer Register DMA_DBP For more information on the DMA Descriptor Base Pointer Register see Direct Memory Access on page 9 1 Figure 12 17 UARTx Receive DMA Next Descriptor Pointer Registers...

Page 548: ...x Receive DMA Descriptor Ready Registers Table 12 20 UARTx Receive DMA Descriptor Ready Register MMR Assignments Register Name Memory Mapped Address UART0_DESCR_RDY_RX 0xFFC0 1A0C UART1_DESCR_RDY_RX 0...

Page 549: ...e DMA IRQ Status Registers Table 12 21 UARTx Receive DMA IRQ Status Register MMR Assignments Register Name Memory Mapped Address UART0_IRQSTAT_RX 0xFFC0 1A0E UART1_IRQSTAT_RX 0xFFC0 1E0E 0 0 0 0 0 0 0...

Page 550: ...iptor Base Pointer Register DMA_DBP For more information on the DMA Descriptor Base Pointer Register see Direct Memory Access on page 9 1 Figure 12 20 UARTx Transmit DMA Current Descriptor Pointer Reg...

Page 551: ...n Completion RO Data Size Bit 0 RO Autobuffer 0 Autobuffer mode disabled 1 Autobuffer mode enabled 0 Memory read 1 Memory write 0 No interrupt generation 1 Generate interrupt on completion This bit is...

Page 552: ...2 shows the UARTx Transmit DMA Start Address High registers Table 12 24 DMA Transfer Sizes Data Size Bit 1 Data Size Bit 0 Transfer Size 0 0 16 bit half word 0 1 32 bit word 1 0 Reserved 1 1 8 bit byt...

Page 553: ...FFC0 1B04 UART1_START_ADDR_HI_TX 0xFFC0 1F04 Figure 12 23 UARTx Transmit DMA Start Address Low Registers Table 12 26 UARTx Transmit DMA Start Address Low Register MMR Assignments Register Name Memory...

Page 554: ...DMA Count Registers Table 12 27 UARTx Transmit DMA Count Register MMR Assignments Register Name Memory Mapped Address UART0_COUNT_TX 0xFFC0 1B08 UART1_COUNT_TX 0xFFC0 1F08 15 14 13 12 11 10 9 8 7 6 5...

Page 555: ...tor Base Pointer Register DMA_DBP For more information on the DMA Descriptor Base Pointer Register see Direct Memory Access on page 9 1 Figure 12 25 UARTx Transmit DMA Next Descriptor Pointer Register...

Page 556: ...12 26 UARTx Transmit DMA Descriptor Ready Registers Table 12 29 UARTx Transmit DMA Descriptor Ready Register MMR Assignments Register Name Memory Mapped Address UART0_DESCR_RDY_TX 0xFFC0 1B0C UART1_DE...

Page 557: ...Infrared Data Association IrDA The physical Figure 12 27 UARTx Transmit DMA IRQ Status Registers Table 12 30 UARTx Transmit DMA IRQ Status Register MMR Assignments Register Name Memory Mapped Address...

Page 558: ...requires external transceivers UART0 Infrared Control Register UART0_IRCR The UART0_IRCR register shown in Figure 12 28 contains bits that con trol all IrDA related features These include the enable...

Page 559: ...riods This results in the final representation of the original 0 as a high pulse of only 3 16 clock periods in a 16 cycle UART clock period The pulse is centered around the middle of the bit time as s...

Page 560: ...16x clock periods The window is wider than the transmitted IrDA pulse to allow for clock frequency discrepancies between the trans mitter and receiver Within this window the receiver incorporates mini...

Page 561: ...is selectable using the IRPOL bit Figure 12 30 gives examples of each polarity type IRPOL 0 assumes that the receive data input idles 0 and each active 1 transition corresponds to a UART NRZ value of...

Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...

Page 563: ...tem can be easily interfaced to a 3 3V Revision 2 2 compliant PCI bus Host to PCI bridge in which ADSP BF535 processor resources the core internal and external memory and the memory DMA controller pro...

Page 564: ...z at 3 3 V and is asynchronous with respect to the ADSP BF535 processor system clock The PCI bus multiplexes data transfers on the same bus used for address transfers and supports a maximum transfer r...

Page 565: ...35 processor can also support a PCI USB bridge function As a PCI device the PCI controller can use the Memory DMA controller to perform DMA transfers as required by the PCI host PCI Host Function The...

Page 566: ...this function Pull up resistors on signals that may not always be driven to a valid state Non volatile memory The intent is that EE flash PROM require ments for a PCI initiator can be supported throu...

Page 567: ...Memory Bank 3 16 MB 128 MByte x2FFF FFFF ASYNC Memory Bank 2 64 MByte x2800 0000 x2C00 0000 xE000 0000 xEEFE FFFF xEEFF FFFC PCI IO Space 64 KByte PCI Config Registers 64 KByte xEEFF FF00 xEEFF FFFF P...

Page 568: ...iates a PCI transaction For memory and I O accesses the address put onto the PCI Address Data bus PCI AD is a concatenation of the upper bits of the Base Address pointer MBAP or IBAP and the lower bit...

Page 569: ...e write is again delayed Three status bits have been provided in the PCI_STAT register that let you interrogate whether the TX FIFO is full or empty and whether the transaction FIFO is full The PCI Ma...

Page 570: ...erminates the cycle with a target abort The requested PCI target responds with a PCI_DEVSEL but does not follow with PCI_TRDY or PCI_STOP to allow the cycle to com plete The master abandons the cycle...

Page 571: ...he data CPLB entry or entries used to describe the PCI memory and I O spaces must have the CPLB_L1_CHBL bit cleared Note that core instruction fetch from PCI space is not supported The PCI protocol is...

Page 572: ...im the transaction as the intended target Each bit of the mask registers must be set to 1 by the processor core start ing with the uppermost bit bit 31 To prevent the core from claiming either memory...

Page 573: ...tried until space is available for the next word Two status bits in the PCI_STAT register are set whenever the Slave TX Data FIFO or Slave RX Data FIFO have data written into them These bits are stick...

Page 574: ...rface supports single 32 bit word memory and I O accesses It also supports memory bursts of any number of 32 bit words However the data FIFOs for inbound accesses are only 8 words deep and if the writ...

Page 575: ...acts as the sys tem processor with the PCI interface acting as its host to PCI bridge The ADSP BF535 processor is put into host mode by setting the Host Device Switch bit in the PCI_CTL register In ho...

Page 576: ...for the asynchronous memory and one for SDRAM memory that specify how much of each of these spaces is available to PCI For the asynchronous memory region the size field is 2 bits and specifies the num...

Page 577: ...le for the ADSP BF535 processor to assign to different devices on the bus Memory however must be allocated with care The default con figuration of the PCI_HMCTL register disables all ADSP BF535 proces...

Page 578: ...ts some registers in the PCI clock domain PCI registers that are not affected by a PCI reset are PCI_CFG_DIC PCI_CFG_VIC PCI_CFG_STAT PCI_CFG_CMD PCI_CFG_MLT PCI_CFG_CLS PCI_CFG_MBAR and PCI_CFG_IBAR...

Page 579: ...et bit in the PCI_STAT register is set when the PCI_RST line is asserted Interrupt Behavior and Control All four interrupt lines from PCI INTA INTD have associated sticky status bits in the PCI_STAT r...

Page 580: ...group of registers is described in the sections that follow Bus Operation Ordering Processor core accesses to the PCI interface always occur in the order that the processor core initiated the system...

Page 581: ...ese registers is 0xFFC0 4000 0xFFC0 43FF Refer to System MMR Assignments on page B 1 for the address of a particular register The PCI peripheral also has several registers mapped into the memory space...

Page 582: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCI Bridge Control Register PCI_CTL 0 Device operation 1 Host operation PCI Enable Bit Fast Back to Back Enable INTA to PCI Enable Host Device Switch INTA to PCI RST to PC...

Page 583: ...0 No interrupt 1 Interrupt signaled on INTB PCI Slave RX FIFO got Data PCI Slave TX FIFO got Data 0 No data 1 Data written to slave transmit FIFO 0 No data 1 Data written to slave receive FIFO 0 0 IN...

Page 584: ...Controller Register PCI_ICTL The bits in this register shown in Figure 13 5 enable the flags in PCI Sta tus register except the PCI Master Queue Full bit and the PCI Master TX FIFO Empty bit Those two...

Page 585: ...dress Register PCI_IBAP This register shown in Figure 13 7 is the I O base address pointer Figure 13 6 PCI Outbound Memory Base Address Register Figure 13 7 PCI Outbound I O Base Address Register 31 3...

Page 586: ...utgoing PCI configuration space transfers The register can then be used for Type 1 or Type 0 addresses with IDSELs on the upper bits or a combination of the two address types if IDSEL generation is mo...

Page 587: ...ed on a boundary that is an inte ger multiple of this size The MMR address for this register is 0xFFC0 4018 Its reset value is 0x0000 0000 PCI Inbound I O Base Address Register PCI_TIBAP This register...

Page 588: ...the respective memory areas made available to the PCI bus when the PCI peripheral functions as a PCI device The corresponding BARs are part of the PCI configuration space and are programmed by the PC...

Page 589: ...for access into the Blackfin processor s memory space using I O space PCI transactions The PCI_DIBARM register is shown in Figure 13 10 It is filled by the Blackfin processor core with 1s starting fr...

Page 590: ...ernal bus masters During configuration the PCI host processor loads the PCI_CFG_IBAR reg ister using this mask setting the base address in PCI I O space of the window into the Blackfin processor s mem...

Page 591: ...host mode Program this register before enabling the PCI in device mode For more information see the PCI Local Bus Specifica tion Rev 2 2 Figure 13 11 PCI Configuration Device ID Register 31 30 29 28 2...

Page 592: ...sters It is not used in host mode Program this register before enabling the PCI in device mode For more information see the PCI Local Bus Specifica tion Rev 2 2 Figure 13 12 PCI Configuration Vendor I...

Page 593: ...8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 PCI Configuration Status Register PCI_CFG_STAT 0 Not fast back to back capable 1 Fast back to back capable 00 Fast 01 Medium 10 Slow 11 Reserved 0 No...

Page 594: ...master 0 Disable response to memory accesses 1 Memory decoders respond to accesses I O Space Memory Space Bus Master Fast Back to Back Enable SERR Enable Stepping Control RO Parity Error Response 0 D...

Page 595: ...FG_CC This register shown in Figure 13 15 holds the class code from the PCI configuration registers It is not used in host mode Program this register before enabling the PCI in device mode For more in...

Page 596: ...is not used in host mode Program this register before enabling the PCI in device mode For more information see the PCI Local Bus Specifica tion Rev 2 2 Figure 13 16 PCI Configuration Revision ID Regi...

Page 597: ...e PCI configuration registers The PCI core does not support BIST For more information see the PCI Local Bus Specification Rev 2 2 Figure 13 17 PCI Configuration BIST Register 31 30 29 28 27 26 25 24 2...

Page 598: ...y timer from the PCI configuration registers It is always writable except where reserved and for two hardwired bits Write to this register only during PCI system configuration in host mode In device m...

Page 599: ...the PCI Local Bus Specification Rev 2 2 Figure 13 19 PCI Configuration Memory Latency Timer Register Figure 13 20 PCI Configuration Cache Line Size Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 600: ...e Configuration software detects the size requested by looking at the number of writable upper bits and places a base address in this space This register is unused in Host mode For more information se...

Page 601: ...The configuration software detects the size by looking at the number of writable upper bits and places a base address in this space This register is unused in Host mode For more information see the P...

Page 602: ...figuration Subsystem Vendor ID Register PCI_CFG_SVID The PCI_CFG_SVID register shown in Figure 13 24 holds the subsystem vendor ID from the PCI configuration registers Program this register before ena...

Page 603: ...figuration Subsystem Vendor ID Register Figure 13 25 PCI Configuration Maximum Latency Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7...

Page 604: ...errupt pin value from the PCI configuration registers For more information see the PCI Local Bus Specification Rev 2 2 Figure 13 26 PCI Configuration Minimum Grant Register Figure 13 27 PCI Configurat...

Page 605: ...host mode The PCI core asserts DEVSEL and claims the transaction for any region indicated as enabled in this register The asynchronous memory access is valid only if the Async Mem Access Enable bit is...

Page 606: ...s at the board level and lowers overall system power consumption Figure 13 29 PCI Host Memory Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13...

Page 607: ...mains can operate at different voltage levels In general it is recommended that power be applied to both domains at the same time or to the I O power domain first then to the internal logic power doma...

Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...

Page 609: ...s memory mapped registers an interrupt subsystem a configuration and clock control for the UDC and a DMA controller for the transfer of USB endpoint data between system memory and the USB On the syste...

Page 610: ...ocessor s USB peripheral includes Eight physical USB endpoints The ADSP BF535 processor can support one configuration with the configuration having two interfaces and each interface having two alterna...

Page 611: ...ected when there is excessive SPORT activity coupled with USB transactions on the DAB bus This condition could also occur on an external memory access using MemDMA to a high latency external memory US...

Page 612: ...and flow control So far as the device is concerned it can receive transfer requests for any endpoint at any time Depending on the bus loading the USB host may request packets back to back or it may re...

Page 613: ...buffering of each endpoint s data resulting in streaming operation on the USB The registers support the ability of the USB to perform packet retries and the ability to break large data buffers into in...

Page 614: ...erial link and presents data and command transactions to the application by means of a simple appli cation bus Figure 14 1 USBD Module Block Diagram PAB_HCLK DOMAIN BUS CLOCK FRONT END INTERFACE TRANS...

Page 615: ...gated clocks The gated clock control circuit ensures error free clocking to the UDC module in a DFT design for testability friendly way Transaction Decode and Clock Synchronization Block The transact...

Page 616: ...the interrupt subsystem in USBD to the ADSP BF535 processor s inter rupt controller Memory Interface Block The Memory Interface module connects the USB endpoints to specific memory resources in the s...

Page 617: ...address of the USBD module s access space within system memory Burst count for the current transfer Direction for the current transfer Status of the DMA module In normal operation the device software...

Page 618: ...r supported packet sizes Bulk Interrupt Isochronous Control Any endpoint 1 through 7 can be defined as Bulk Interrupt or Isochro nous In accordance with the USB specification endpoint 0 is always defi...

Page 619: ...enerally used for raw audio or video data During each 1 0 ms frame isochronous data transfers are given a guaran teed percentage of the USB s bandwidth Because of this guaranteed bandwidth the isochro...

Page 620: ...DESCRIPTOR standard requests All class and vendor requests Device software must monitor the interrupts to determine when a setup packet has been received on a control endpoint and respond accordingly...

Page 621: ...evice After 3 ms of inactivity on the bus the device automatically drops into a suspended state After the USB host generates resume signal ing on the bus the device reenters its active state and resum...

Page 622: ...s configured to support full speed operation at all times The external transceiver must also be configured to support the fast slew rate of the full speed USB mode Registers This section describes the...

Page 623: ...register USBD_GINTR Global Interrupt Mask register USBD_GMASK The DMA registers handle configuration and control of the DMA master channel embedded within the module These registers are described in l...

Page 624: ...ter USBD_ID This register shown in Figure 14 3 is used to identify the module to the system Using binary coded decimal the USBD_SPEC field indicates the ver sion of the USB specification that the modu...

Page 625: ...chanism for software to wait for the arrival of a specific USB frame number This feature is typi cally used with isochronous endpoints for synchronization between the Figure 14 3 USB Device ID Registe...

Page 626: ...DC module after hard reset events The EpBuf structures hold configuration information for each possible end point on the device including the configuration number packet size direction type and the in...

Page 627: ...the USB interface number It is updated when the USB host sends a SET_INTERFACE request to the device It changes along with the USBD_AIF field The USBD_AIF field contains the alternate interface numbe...

Page 628: ...number within the USBD hardware It may not match the actual USB endpoint number due to mapping which occurs in the UDC hardware Figure 14 7 USBD Module Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 629: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBD Module Configuration and Control Register USBD_CTRL USBD_EP2STALL 0 USBD module disabled 1 USBD module enabled USBD_EP3STALL USBD_UDCRST USBD_EP0STALL USBD_EP1STALL U...

Page 630: ...may be masked or unmasked at any time When masked an interrupt does not affect the state of the module s USBD_INTR output To determine the interrupt status software must poll a masked interrupt The i...

Page 631: ...oint 5 0 No interrupt pending for endpoint 4 1 Interrupt pending for endpoint 4 0 No interrupt pending for endpoint 3 1 Interrupt pending for endpoint 3 0 No interrupt pending for endpoint 2 1 Interru...

Page 632: ...mas ter channel The USBD_DMABC bit is the DMA buffer clear bit It forces the DMA FIFO to be cleared Writing a 1 initiates and holds the buffer in a clear state A write of 0 must follow before normal o...

Page 633: ...ow Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA Master Channel Configuration Register USBD_DMACFG DMA configuration register USBD_IOE bit has no effect on DMA tra...

Page 634: ...shown in Figure 14 14 holds the DMA count for the cur rent transfer This reads back the number of bytes pending for the DMA transfer on the currently selected endpoint and its value ranges from 0 to 4...

Page 635: ...endpoint x All bits are write 1 to clear The USBD_MSETUP bit is set when a UDC_SETUP interrupt is pending and another setup packet is received This condition can occur if the USB device s ACK of a set...

Page 636: ...ronous transfers this interrupt does not assert if the packet transferred with errors Software can use the USBD_PC and USBD_TC interrupts along with the endpoint configuration registers to determine t...

Page 637: ...TR1 0xFFC0 448A USBD_INTR2 0xFFC0 4494 USBD_INTR3 0xFFC0 449E USBD_INTR4 0xFFC0 44A8 USBD_INTR5 0xFFC0 44B2 USBD_INTR6 0xFFC0 44BC USBD_INTR7 0xFFC0 44C6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0...

Page 638: ...0xFFC0 448C USBD_MASK2 0xFFC0 4496 USBD_MASK3 0xFFC0 44A0 USBD_MASK4 0xFFC0 44AA USBD_MASK5 0xFFC0 44B4 USBD_MASK6 0xFFC0 44BE USBD_MASK7 0xFFC0 44C8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0...

Page 639: ...ess clearing this bit does not stop the current packet transfer but it does prevent succeeding packets in a multipacket transfer from occur ring For example consider a 64 byte packet 128 byte count If...

Page 640: ...pped Address USBD_EPCFG0 0xFFC0 4484 USBD_EPCFG1 0xFFC0 448E USBD_EPCFG2 0xFFC0 4498 USBD_EPCFG3 0xFFC0 44A2 USBD_EPCFG4 0xFFC0 44AC USBD_EPCFG5 0xFFC0 44B6 USBD_EPCFG6 0xFFC0 44C0 USBD_EPCFG7 0xFFC0...

Page 641: ...the USB the USBD_OFFSET increments by the packet size For the USB Endpoint x Address Offset registers and the USB Endpoint x Buffer Length registers USBD_EPLENx it is assumed that soft ware is keeping...

Page 642: ...er is partitioned into a number of individual packet transfers at the endpoint s maximum packet size For non isochronous endpoints this field decrements by the packet size as each packet is transferre...

Page 643: ...register is not a memory mapped register Figure 14 20 USB Endpoint x Buffer Length Registers Table 14 5 USB Endpoint x Buffer Length Register MMR Assignments Register Name Memory Mapped Address USBD_E...

Page 644: ...cal endpoints one configura tion two interfaces and two alternate interfaces Given this configuration the EPNUM field physical endpoints can hold values from 0 to 7 the EP_CONFIG field can be 0 or 1 t...

Page 645: ...ts the DMA master channel and each endpoint Figure 14 21 UDC Endpoint Buffer Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 646: ...interrupt as part of their synchronization mechanism USBD_CFG USB Configuration Change The USBD_CFG interrupt indicates to the device that a configuration change event occurred on the USB The host ha...

Page 647: ...le in progress DMA transfers Software can monitor the USBD_RSTSIG bit in the USBD_STAT register to monitor the state of reset signaling USBD_SUSP Device Suspended This interrupt asserts when the USB d...

Page 648: ...ch condition between the Current USB Frame Number register USBD_FRM and the Match Value for USB Frame Number register USBD_FRMAT After hard reset this interrupt is set because both the USB frame numbe...

Page 649: ...DMA bus error Data misalignment Illegal memory access Data Misalignment Misalignment of address to data size occurs when the USBD_OFFSET USBD_EPADRx is not word aligned If the address is misaligned to...

Page 650: ...transfer completes on the current endpoint Because the USB protocol does not maintain a transfer count the end of a transfer is assumed whenever a short packet is transferred on an endpoint The USB pr...

Page 651: ...ld happen when the USB device s ACK of the first setup packet is not received by the USB host and the USB host retransmits the command USBD_MERR Memory Controller Error This interrupt covers the case...

Page 652: ...oint on the device there can be more than one EpBuf For example it is possible to have endpoint 1 in USB configu ration 1 as well as endpoint 1 in USB configuration 2 While the two endpoints have the...

Page 653: ...1 until the download process is complete 3 Wait for the USBD_RDY bit to return to 1 Depending on the clock frequency of the PAB the wait can be 30 or more clock periods 4 Go back to step 2 After all...

Page 654: ...O USBD_DMABHI in system memory and enable the DMA 4 Program the endpoint registers for endpoint 0 in order to receive commands from the USB host a USBD_EPCFG0 USBD_MAX Endpoint s maximum packet size U...

Page 655: ...programming of the endpoint configuration registers to support USB data transfers It includes a number of cases typi cally encountered such as Bulk IN OUT Isochronous IN OUT and Control transfers Exce...

Page 656: ...device recognizes the shortened data packet as the end of a group of packets If the data transfer ends on a packet boundary that is a 64 byte transfer 8 byte packet size the data source sends a last...

Page 657: ...l as interrupt and control transfers are based around a limited set of packet sizes The USB 1 1 specification defines valid sizes of 8 16 32 and 64 bytes Each USB endpoint is assigned one of these pos...

Page 658: ...es at various locations in the 2 KB buffer space This can be a single 1023 byte isochronous endpoint buffer or many 16 byte bulk endpoint buffers Bulk In Assume 64 byte packet size packet buffer locat...

Page 659: ...Update USBD_EPADRx and USBD_EPLENx to point to the next buffer of data then set USBD_ARM 1 to re arm the endpoint If no more data is to be sent clear interrupts program USBD_BC 0 and set UDBD_ARM 1 W...

Page 660: ...PxINTR interrupts If USBD_BCSTAT and not USBD_TC Clear interrupts then go back to step 2 Update USBD_EPADRx and USBD_EPLENx to point to a new data buffer and then set USBD_ARM 1 to re arm the endpoint...

Page 661: ...g up the transfer for the next frame as soon as the USBD_TC interrupt is received for the current frame For USB OUT endpoints this translates to putting a buffer in place as soon as the USBD_TC interr...

Page 662: ...buffer size 0x80 one packet Programming flow is 1 Clear all interrupts Write USBD_EPINTRx all ones Write USBD_EPxINTR bit of USBD_GINTR register 1 2 Unmask interrupts USBD_MASKx USBD_BCSTAT 0 USBD_PC...

Page 663: ...mmer Software must determinate whether this is an error or merely a warning 5 Go back to step 2 to prepare for the next frame s data transfer Iso Out Assume 1023 byte packet size packet buffer located...

Page 664: ...etries are performed Control Transfers In general Control endpoints usually endpoint 0 operate like Bulk end points However Control endpoints are bidirectional and follow a special protocol that allow...

Page 665: ...BD_TYP 00 USBD_DIR 0 OUT direction The USBD_MAX field is programmed to match the endpoint s maximum packet size The USBD_ARM bit is set to 1 4 Monitor the USBD_SETUP interrupt 5 On receipt of a USBD_S...

Page 666: ...TUP interrupt read the setup packet from the memory buffer and decode the command If the command is valid execute it If the wLength field of the setup packet is nonzero then a data phase is associated...

Page 667: ...its internal buffer and must figure out which is the real one before moving on and processing the command The USBD module includes several features to help deal with this situa tion The features are T...

Page 668: ...errors on individual data packets transparently without software intervention The USB protocol supports packet retries for Bulk Control and Interrupt packets In cases where a catastrophic problem occu...

Page 669: ...module still asserts the USBD_TC but it does not assert the USBD_PC In this way the application can detect and compensate for errors Reset Signaling Detected on USB USB reset signaling is generated by...

Page 670: ...the USB specification and is supposedly guaranteed by the system software on the USB host Because no USB compliance tests exist for USB hosts the 10 ms window cannot be guaranteed across all operating...

Page 671: ...es is readily available for USB product developers USB Device Class Specifications www usb org The common class specifications provide a framework in which device developers can make use of standardiz...

Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...

Page 673: ...terrupt can be generated according to the state of the pin either high or low an edge transition low to high or high to low or on both edge transitions low to high and high to low Input sensitivity is...

Page 674: ...m memory mapped registers MMRs The addresses of the programmable flag MMRs appear in Appendix B Core access to the flag configuration regis ters is through the system bus Flag Direction Register FIO_D...

Page 675: ...igured as an output Writing 0x0001 to the Flag Set register drives a logic 1 on the PF 0 pin without affecting the state of any other PFx pins Writing 0x0001 to the Flag Clear register drives a logic...

Page 676: ...et PF15 Set PF1 Set PF2 Set PF3 Set PF4 Set PF5 Write 1 to set Set PF6 Set PF7 Set PF11 Set PF10 Set PF9 Set PF8 Reset The value of PF pins after reset 0xFFC0 2406 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 677: ...lear register see Figure 15 4 Figure 15 5 Figure 15 6 and Figure 15 7 Each PFx pin is represented by a bit in each of the four registers Writing a 1 to a bit in a mask set register enables interrupt g...

Page 678: ...PF5 Interrupt For all bits 1 Enable Enable PF6 Interrupt Enable PF7 Interrupt Enable PF11 Interrupt Enable PF10 Interrupt Enable PF9 Interrupt Enable PF8 Interrupt Reset 0x0000 0xFFC0 240A 15 14 13 12...

Page 679: ...F14 Interrupt Enable PF15 Interrupt Enable PF1 Interrupt Enable PF2 Interrupt Enable PF3 Interrupt Enable PF4 Interrupt Enable PF5 Interrupt For all bits 1 Enable Enable PF6 Interrupt Enable PF7 Inter...

Page 680: ...t generation in FIO_MASKA_S and FIO_MASKA_C Yes No Input No Input Yes Yes Yes Yes Yes Yes Yes FLAG INTERRUPT A OCCURS FLAG INTERRUPT B OCCURS START Is FlagN set as an output in FIO_DIR Is FlagN assert...

Page 681: ...ffect on PFx pins that are defined as outputs The contents of this register are cleared at reset defaulting to active high polarity Figure 15 9 Flag Polarity Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 682: ...ed at reset defaulting to level sensitivity Flag Set on Both Edges Register FIO_BOTH The Flag Set on Both Edges register shown in Figure 15 11 is used to enable interrupt generation on both rising and...

Page 683: ...core and the system clock Changes in the state of PFx pins have a latency of 3 SCLK cycles before being detectable by the processor When configured for level sensitive interrupt generation there is a...

Page 684: ...15 12 ADSP BF535 Blackfin Processor Hardware Reference SCLK cycle of latency is introduced giving a total latency of 5 SCLK cycles between the time the edge is asserted and the time that the core prog...

Page 685: ...to generate periodic interrupts for a variety of system timing functions The watchdog timer can be used to implement a software watchdog func tion A software watchdog can improve system availability...

Page 686: ...ifier from the TIMERx_COUNTER TIMERx_PERIOD and TIMERx_WIDTH registers refer ring to each of these MMRs as a 32 bit entity Table 16 1 shows the true register mappings that should be used in user code...

Page 687: ...IMER2_STATUS 0xFFC0 2020 Timer2 Status register TIMER2_CONFIG 0xFFC0 2022 Timer2 Configuration register TIMER2_COUNTER_LO 0xFFC0 2024 Timer2 Counter register Low Word TIMER2_COUNTER_HI 0xFFC0 2026 Tim...

Page 688: ...counting three peripheral clock cycles after the TIMENx bit is set Setting the timer TIMDISx bit stops the timer without waiting for any additional event Each TIMERx_STATUS register also contains a Ti...

Page 689: ...Clear Timer0 interrupt flag 0 No Timer1 interrupt occurred 1 Timer1 interrupt occurred TIMDIS2 Timer2 Disable RO TIMEN2 Timer2 Enable RO 1 Timer2 enabled if TIMEN2 1 1 Timer2 enabled if TIMDIS2 1 TIMD...

Page 690: ...mer2 Enable RO 1 Timer2 enabled if TIMEN2 1 1 Timer2 enabled if TIMDIS2 1 TIMDIS1 Timer1 Disable W1C TIMEN1 Timer1 Enable W1S TIMDIS0 Timer0 Disable RO TIMEN0 Timer0 Enable RO IRQ2 Timer2 Interrupt RO...

Page 691: ...eparate the IRQx clear command from the RTI instruction an Figure 16 3 Timer2 Status Register 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 0 Timer2 Status Register...

Page 692: ...set the UARTy RX pin is cap tured instead of the TMRx pin Timer 0 alternatively captures UART0 Timer 1 alternatively captures UART1 and Timer 2 alternatively captures UART1 Figure 16 4 Timer Configura...

Page 693: ...isabling the timers Figure 16 5 Timer Enable and Disable Timing SCLK PWM_OUT SCLK COUN T M C OUN T M 1 C OUN T M 1 COUN T M 1 Timer Enable Se t TIM ENx Time r Ena bled PER IOD 0x4 WID TH 0x1 PU LSE_H...

Page 694: ...s WDTH_CAP These registers are read only registers and contain the captured period value EXT_CLK These registers are write only registers and contain the maximum timer external count Figure 16 6 Timer...

Page 695: ...value EXT_CLK Not used Timer Counter Registers TIMERx_COUNTER These read only registers retain their state when disabled When enabled the counter is reinitialized from the Timer Period and Timer Width...

Page 696: ...ues 5 Repeat from step 1 if they are not equal In External Event Capture mode EXT_CLK the TMRx pin RX1 or RX0 for autobaud detection is used to clock the timer counter The counter is initialized with...

Page 697: ...e timer is clocked internally by SCLK Depending on the state of the PERIOD_CNT bit in TIMERx_CONFIG PWM_OUT either generates pulse width modulation waveforms or generates a single pulse on the TMRx pi...

Page 698: ...imer Width registers are programmed with the values of the timer count period and the pulse width modulated output pulse width When the timer is enabled in this mode the TMRx pin is pulled to a deas s...

Page 699: ...R0_PERIOD_LO W P0 R1 L PO L lo TIMER0_WIDTH_HI W P0 R2 H PO L lo TIMER0_WIDTH_LO W P0 R2 L PO L lo TIMER0_STATUS R0 L 0x0100 W P0 R0 L SSYNC If enabled a timer interrupt is generated at the end of eac...

Page 700: ...egisters As seen in Figure 16 9 this causes the generation of one incorrect period if the write to the TIMERx_WIDTH_LO register occurs before the ongoing pulse width expires This is very likely becaus...

Page 701: ...leared PWM_OUT generates a single pulse on the TMRx pin This mode can also be used to implement a precise delay The pulse width is defined by the Timer Width register and the Timer Period register is...

Page 702: ...the timer transfers the current 32 bit value of TIMERx_COUNTER into TIMERx_PERIOD The TIMERx_COUNTER register is reset to 0x0000 0001 and the timer continues counting until it is either disabled or t...

Page 703: ...is set indicating a count over flow IRQx and OVF_ERRx are sticky bits and software must clear them explicitly Because of synchronizer latency insert two NOP instructions between set ting WDTH_CAP and...

Page 704: ...tection might not return sufficient results without additional analog signal conditioning Therefore it is strongly recommended to measure signal periods instead For example predefine ASCII character 4...

Page 705: ...FFFF period Every subsequent rising edge increments the count register After reaching the count value 0xFFFF FFFE the IRQx bit is set and an interrupt is generated The next rising edge reloads the co...

Page 706: ...ister is set then the TCOUNT register is reloaded with the contents of the TPERIOD register and the count begins again The core timer can be put into low power mode by clearing the TMPWR bit in the TC...

Page 707: ...imer in low power mode 1 Active state Timer can be enabled using the TMREN bit Meaningful only when TMPWR 1 0 Disable timer 1 Enable timer TINT TAUTORLD Sticky status bit 0 Timer has not generated an...

Page 708: ...he counter register decrements once every clock cycle If TSCALE is 1 the counter decrements once every 2 cycles Figure 16 16 Core Timer Period Register Figure 16 17 Core Timer Scale Register Core Time...

Page 709: ...lue for the watchdog timer by writing the count value into the Watchdog Count register WDOG_CNT 2 Copy the count value from WDOG_CNT into the Watchdog Status register WDOG_STAT by executing a write to...

Page 710: ...stops counting and the event selected in the Watchdog Control reg ister WDOG_CTL is generated Values cannot be stored directly in WDOG_STAT but are instead copied from WDOG_CNT When the processor exe...

Page 711: ...ely configured to unmask that interrupt If the generation of watchdog events is disabled the watchdog timer operates as described except that no event is generated when the watchdog timer expires The...

Page 712: ...timer For more information see Software Resets and Watchdog Timer on page 3 14 The TRO bit can also be manually cleared by writing a 1 to it When the processor is in Emulation mode the watchdog timer...

Page 713: ...is divided down to a 1 Hz signal by a prescaler which can be bypassed When bypassed the RTC is clocked at the 32 768 kHz crystal rate In normal operation the prescaler is enabled The primary function...

Page 714: ...n the stopwatch interrupt is enabled and the specified number of minutes have elapsed the RTC generates an interrupt The RTC can also generate an interrupt once every second minute and day Each of the...

Page 715: ...write to the same register without waiting for the previous write to complete Subsequent writes to the same register are ignored if the previous write is not complete Do not read a register that has b...

Page 716: ...Setting then immediately clearing the Prescaler Enable bit could result in its being set Clear all flags at power up and when setting the RTC Status regis ter RTC_STAT the RTC Alarm register RTC_ALARM...

Page 717: ...the slow clock Use the Seconds 1 Hz Event flag to check for the first edge of the RTC clock The Seconds 1 Hz interrupt may also be used but this causes a delay of up to two seconds Write Pending Statu...

Page 718: ...e using this flag value or enabling its interrupt Day Alarm Event Flag Same as Alarm Wait for the RTC_STAT RTC_ALARM and RTC_SWCNT fields to be valid before enabling the alarm interrupt so that no spu...

Page 719: ...egister RTC_STAT RTC Memory Mapped Registers MMRs This section describes the memory mapped registers for the RTC RTC Status Register RTC_STAT The RTC Status register shown in Figure 17 1 is used to re...

Page 720: ...ck if enabled The minutes interrupt is generated as the minute counter counts through sixty 1 Hz clock ticks The 24 hour interrupt occurs once per 24 hour period at midnight Any of these interrupts ca...

Page 721: ...a 1 to the respective bit location except for the Write Pending Status bit which is read only Writes of 0 to any bit of the register have no effect This register is cleared at reset Figure 17 2 RTC I...

Page 722: ...tween 0 and 255 minutes Figure 17 3 RTC Interrupt Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Stopwatch Event Flag 0 No event 1 Event occurred Alarm Event Fla...

Page 723: ...e day interrupt occurs whenever the day hour minute and second fields match those of the RTC Status register Figure 17 4 RTC Stopwatch Count Register Figure 17 5 RTC Alarm Register 15 14 13 12 11 10 9...

Page 724: ...t the proper rate Do not disable the prescaler by clearing the bit in RTC_FAST with out making sure that there are no writes in progress Do not switch between fast and slow mode during normal operatio...

Page 725: ...em MMR For more information see Core Clock System Clock Ratio Control on page 8 5 The external memory space is shown in Figure 18 1 Four of the memory regions are dedicated to SDRAM support SDRAM inte...

Page 726: ...000 0x2400 0000 External Memory Map SDRAM Memory Bank 2 16 MB 128 MByte SDRAM Memory Bank 3 16 MB 128 MByte 0x2FFF FFFF ASYNC Memory Bank 2 64 MByte 0x2800 0000 0x2C00 0000 0xE000 0000 0xEEFE FFFF 0xE...

Page 727: ...enerate an interrupt from PCI or a DMA channel depending on where the access originated The PCI space shown at the top of the external memory map is supported by the PCI Controller not the EBIU For mo...

Page 728: ...r the DMA bus or mastered by the MemDMA controller External Mastered Bus EMB mastered by the PCI bridge Peripheral Access Bus PAB mastered by the SBIU on behalf of system MMR requests from the core or...

Page 729: ...r subse quent requests if both buses are requesting EBIU access External Memory Interfaces Both the AMC and the SDC share the external interface address and data pins as well as some of the control si...

Page 730: ...ADSP BF535 Blackfin Embedded Processor Data Sheet for specific timing informa tion between the AOE and ARE signals to deter mine which interface signal should be used in your system ARDY I Asynchronou...

Page 731: ...utput on SDQM 3 and should be connected to SDRAM A 0 pin SMS 3 0 O Memory select pin of external memory bank configured for SDRAM Connect to SDRAM s CS chip select pin SA10 O SDRAM A10 pin SDRAM inter...

Page 732: ...d SDC sections later in this chapter In addition to the EBIU control and status registers system MMRs described in this chapter the clock distributed to the EBIU has a dedicated enable located in the...

Page 733: ...more informa tion refer to PCI Bus Interface on page 13 1 If a DMA master requested the faulting bus operation then the bus error is captured in that controller and can optionally generate an interru...

Page 734: ...s to valid AMC addresses The asynchronous memory signals are defined in Table 18 2 on page 18 6 The timing of these pins is programmable to allow a flexible interface to devices of different speeds Fo...

Page 735: ...single external transaction When 32 bit packing is enabled all 32 bit transactions are processed with a single transfer Figure 18 3 Asynchronous Memory Global Control Register 15 14 13 12 11 10 9 8 7...

Page 736: ...ogrammed using these four parameters Setup the time between the beginning of a memory cycle AMS x low and the read enable assertion ARE low or write enable asser tion AWE low Read Access the time betw...

Page 737: ...et these synchronous specifications could result in meta stable behav ior internally The ADSP BF535 processor s CLKOUT signal should be used to ensure synchronous transitions of ARDY The ARDY pin must...

Page 738: ...nsaction completes if ARDY sampled high Bank 1 ARDY enable 0 Ignore ARDY for accesses to this memory bank 1 After access time countdown use state of ARDY to deter mine completion of access Reset 0xFFC...

Page 739: ...saction completes if ARDY sampled high Bank 3 ARDY enable 0 Ignore ARDY for accesses to this memory bank 1 After access time countdown use state of ARDY to deter mine completion of access Reset 0xFFC2...

Page 740: ...tions of the type R0 P0 Read from external memory where P0 points to a location in external memory or P0 R0 Write to external memory Asynchronous Reads Figure 18 6 shows two core initiated asynchronou...

Page 741: ...me memory bank is queued internally the AMC appends the programmed number of memory transition time cycles Figure 18 6 Core Initiated Asynchronous Read Bus Cycles Setup 3 cycles Read Access 2 cycles T...

Page 742: ...t the start of the setup period AMS x the address bus data buses and ABE 3 0 become valid At the beginning of the write access period AWE asserts At the beginning of the hold period AWE deasserts Afte...

Page 743: ...ta buses and ABE 3 0 become valid At the beginning of the write access period AWE asserts At the beginning of the hold period AWE deasserts After the hold period AMS x deasserts Figure 18 7 Core Initi...

Page 744: ...ess bus data buses and ABE 3 0 become valid At the beginning of the write access period AWE asserts At the beginning of the hold period AWE deasserts After the hold period AMS x deasserts Figure 18 8...

Page 745: ...asserts At the beginning of the hold period AWE deasserts and AMS x remains low for the setup period of the next access The first asynchronous read bus cycle proceeds as At the start of the setup per...

Page 746: ...e hold period read data is sampled on the rising edge of the EBIU clock The ARE pin deasserts after this ris ing edge At the end of the hold period AOE and AMS x deassert Unless another read of the sa...

Page 747: ...rnal memory space occur in bursts of 8 accesses There are 6 SCLK cycles inserted between bursts due to internal bus transactions Figure 18 9 Core Initiated Write and Read Bus Cycles Setup 2 cycles Wri...

Page 748: ...read access 3 cycles hold 3 cycles and transition time 1 cycle The MemDMA access proceeds as At the start of the setup period AMS x the address bus and ABE 3 0 become valid and AOE asserts At the begi...

Page 749: ...d access of 16 words from exter nal memory In this case the asynchronous memory controller is programmed with setup 1 cycle read access 3 cycles hold 1 cycle and transition time 1 cycle This is a smal...

Page 750: ...eriod AWE deasserts At the end of the hold period AMS x deasserts if the transaction is the last in the burst otherwise AMS x remains asserted for the setup period of the next write Adding Additional...

Page 751: ...4 cycles and hold 1 cycle Note that the read access period must be programmed to a minimum of two cycles to make use of the ARDY input Figure 18 13 Inserting Wait States Using ARDY Setup 2 cycles Prog...

Page 752: ...mory arrays All inputs are sampled and all outputs are valid on the rising edge of the SDRAM clock output SCLK 0 or SCLK 1 which has the same timing The SDRAM interface is able to connect to as many a...

Page 753: ...es two clock output pins to drive capacitive loads of larger memory arrays Uses a separate pin SA10 that enables the SDC to precharge SDRAM before issuing an Auto Refresh or Self Refresh command while...

Page 754: ...uring a burst to SDRAM the SDC applies the read or write command every cycle and keeps accessing the data The Burst Length is independent from the performance throughput Burst Stop Command The Burst S...

Page 755: ...g ister EBIU_SDGCTL on page 18 37 CBR CAS before RAS Refresh or Auto Refresh When the SDC refresh counter times out the SDC precharges all four banks of SDRAM and then issues an Auto Refresh command t...

Page 756: ...mode register The write of the SDRAM s mode register is triggered by writing a 1 to the PSSE bit in the SDRAM Memory Global Control register EBIU_SDGCTL and then issuing a read or write transfer to t...

Page 757: ...AM banks are four regions of memory that can be configured to be 16 MB 32 MB 64 MB or 128 MB and are selected by the SMS 3 0 pins Each bank can be selected to be either all 32 bits wide or all 16 bits...

Page 758: ...efresh cycles periodically without external control input The SDC must issue a series of commands including the Self Refresh command to put the SDRAM into this low power mode and it must issue another...

Page 759: ...and and the start of the first Read or Write command The TRCD bit field in the SDRAM Memory Global Control register EBIU_SDGCTL is 3 bits wide and can be pro grammed to be from 1 to 7 clock cycles lon...

Page 760: ...is not directly programmable and is assumed to be equal to tRC The tRC delay must be satisfied by programming the TRAS and TRP fields to ensure that tRAS tRP tRC tXSR Required delay between exiting S...

Page 761: ...ware Reference 18 37 External Bus Interface Unit SDRAM Memory Global Control Register EBIU_SDGCTL The SDRAM Memory Global Control register includes all programmable parameters associated with the SDRA...

Page 762: ...SDRAM Controller SDC 18 38 ADSP BF535 Blackfin Processor Hardware Reference Figure 18 14 shows the SDRAM Global Control register bit definitions...

Page 763: ...les SDRAM tWR in SCLK cycles 00 Reserved 01 11 1 to 3 cycles SDRAM power up sequence 0 Precharge 8 CBR refresh cycles mode register set 1 Precharge mode register set 8 CBR refresh cycles SDRAM power u...

Page 764: ...he SCTLE and SCK1E bits are enabled dur ing reset so SCLK 0 and SCLK 1 are running after reset deasserts If the SDC will not be used the SCTLE and SCK1E bits can be disabled to stop the clocks and red...

Page 765: ...bus is shared between the SDC and the AMC By clearing the PFP bit the amount of bandwidth taken from the AMC is limited when an AMC access needs the external bus prefetching halts and the AMC can use...

Page 766: ...takes many cycles to complete Before executing the SDC power up sequence ensure that the SDRAM receives stable power and is clocked for the proper amount of time as specified by the SDRAM specificati...

Page 767: ...clock buffers for most system memory configurations The SCTLE and SCK1E bits in the SDRAM Memory Global Control register EBIU_SDGCTL provide control for the SDRAM clock control pins The SCTLE bit disa...

Page 768: ...software control the SCTLE and SCK1E bits can be used in conjunc tion with Self Refresh mode to further lower the power consumption However SCTLE must remain enabled at all times when the SDC is need...

Page 769: ...erall system timing requirements systems that employ several SDRAM devices connected in parallel may require buffering between the ADSP BF535 processor and multiple SDRAM devices This buffering genera...

Page 770: ...nd the time it provides the data at its output pins CAS latency does not apply to write cycles The CL bits in the SDRAM Memory Global Control register EBIU_SDGCTL select the CAS latency value CL 00 Re...

Page 771: ...10 pin allows the SDC to enter and exit Self Refresh mode in parallel with any asynchro nous memory access The SA10 pin should be directly connected to the A10 pin of the SDRAM instead of to the ADDR...

Page 772: ...he SDRAM device documentation Selecting the Precharge Delay TRP The tRP value Precharge delay defines the required delay in number of SCLK cycles between the time the SDC issues a Precharge command an...

Page 773: ...between 1 and 3 SCLK cycles may be selected For example TWR 00 Reserved TWR 01 1 clock cycle TWR 10 2 clock cycles TWR 11 3 clock cycles SDRAM Memory Bank Control Register EBIU_SDBCTL The SDRAM Memor...

Page 774: ...RAM external bank 3 column address width 00 8 bits 01 9 bits 10 10 bits 11 11 bits SDRAM external bank 2 enable 0 Disabled 1 Enabled SDRAM external bank 2 size 00 16 MB 01 32 MB 10 64 MB 11 128 MB SDR...

Page 775: ...of the row address The com binations of external bank width X16DE external bank size EBxSZ and column address width EBxCAW which are not supported are also indicated in this table Programming the SDC...

Page 776: ...6 2 32 32 8 Not Supported Reserved 32 16 11 32 16 10 32 16 9 32 16 8 1 IA 23 12 IA 11 10 IA 9 2 IA 1 0 64 16 2 16 128 11 4 IA 26 14 IA 13 12 IA 11 1 IA 0 256 4 4 512 8 2 16 128 10 Not Supported Reserv...

Page 777: ...error bit has been set software must explicitly write a 1 to the bit to clear it 16 64 9 Not Supported Reserved 16 64 8 16 32 11 16 32 10 2 IA 24 13 IA 12 11 IA 10 1 IA 0 64 4 4 128 8 2 16 32 9 1 IA...

Page 778: ...EBIU_SDRRC register before the SDRAM power up sequence is triggered Change this value only when the SDC is idle Figure 18 16 SDRAM Control Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0...

Page 779: ...P in the SDRAM Memory Global Control register in number of clock cycles This equation calculates the number of clock cycles between required refreshes and subtracts the required delay between Bank Act...

Page 780: ...operation of the SDRAM controller is not supported and can produce undesirable behavior Values for RDIV can range from 0x001 to 0xFFF SDRAM External Bank Address Decode The memory address space for ea...

Page 781: ...11 128 01000 Table 18 7 Start Address Calculation SDRAM Bank bank_x_start_addr 28 24 0 00000 1 00000 bank_0_size 4 0 2 00000 bank_0_size 4 0 bank_1_size 4 0 3 00000 bank_0_size 4 0 bank_1_size 4 0 ban...

Page 782: ...connected to a 64 MByte discrete SDRAM memory array EB3E 0 EB3SZ 10 The start addresses for the SDRAM banks and reserved spaces are calcu lated as Figure 18 18 Bank Start Address Calculation 00101 00...

Page 783: ...ulti plexed address into a row address a column address a bank address and the byte data masks for the SDRAM device as shown in Figure 18 19 The lowest bit or bits are mapped to byte data masks the ne...

Page 784: ...ssible configurations of SDRAM sizes and number of chips con nected in parallel are given for each muxing table Note there is no separate ADDR 1 pin on the ADSP BF535 processor The ADDR 1 pin is muxed...

Page 785: ...ddress Pin ADDR 16 IA 26 A 14 ADDR 15 IA 25 A 13 ADDR 14 IA 24 A 12 ADDR 13 IA 23 A 11 SA 10 IA 22 A 10 ADDR 11 IA 21 A 9 ADDR 10 IA 20 A 8 ADDR 9 IA 19 IA 9 A 7 ADDR 8 IA 18 IA 8 A 6 ADDR 7 IA 17 IA...

Page 786: ...DR 14 IA 25 A 12 ADDR 13 IA 24 A 11 SA 10 IA 23 A 10 ADDR 11 IA 22 A 9 ADDR 10 IA 21 IA 10 A 8 ADDR 9 IA 20 IA 9 A 7 ADDR 8 IA 19 IA 8 A 6 ADDR 7 IA 18 IA 7 A 5 ADDR 6 IA 17 IA 6 A 4 ADDR 5 IA 16 IA 5...

Page 787: ...25 A 11 SA 10 IA 24 A 10 ADDR 11 IA 23 IA 11 A 9 ADDR 10 IA 22 IA 10 A 8 ADDR 9 IA 21 IA 9 A 7 ADDR 8 IA 20 IA 8 A 6 ADDR 7 IA 19 IA 7 A 5 ADDR 6 IA 18 IA 6 A 4 ADDR 5 IA 17 IA 5 A 3 ADDR 4 IA 16 IA...

Page 788: ...for CAS SDRAM Address Pin ADDR 13 IA 26 IA 12 A 11 SA 10 IA 25 A 10 ADDR 11 IA 24 IA 11 A 9 ADDR 10 IA 23 IA 10 A 8 ADDR 9 IA 22 IA 9 A 7 ADDR 8 IA 21 IA 8 A 6 ADDR 7 IA 20 IA 7 A 5 ADDR 6 IA 19 IA 6...

Page 789: ...Address for RAS Internal Address for CAS SDRAM Address Pin ADDR 15 IA 26 A 14 ADDR 14 IA 25 A 13 ADDR 13 IA 24 A 12 ADDR 12 IA 23 A 11 SA 10 IA 22 A 10 ADDR 10 IA 21 A 9 ADDR 9 IA 20 IA 9 A 8 ADDR 8...

Page 790: ...DDR 12 IA 24 A 11 SA 10 IA 23 A 10 ADDR 10 IA 22 IA 10 A 9 ADDR 9 IA 21 IA 9 A 8 ADDR 8 IA 20 IA 8 A 7 ADDR 7 IA 19 IA 7 A 6 ADDR 6 IA 18 IA 6 A 5 ADDR 5 IA 17 IA 5 A 4 ADDR 4 IA 16 IA 4 A 3 ADDR 3 IA...

Page 791: ...11 Column Address Pins ADSP BF535 Processor Address Pin Internal Address for RAS Internal Address for CAS SDRAM Address Pin ADDR 13 IA 26 A 12 ADDR 12 IA 25 IA 11 A 11 SA 10 IA 24 A 10 ADDR 10 IA 23 I...

Page 792: ...eros SDQM 2 is 1 and SDQM 3 outputs IA 1 The only time that the SDQM 3 0 pins are high is when bytes are masked during write transfers to the SDRAM banks At all other times the SDQM 3 0 pins are held...

Page 793: ...1 1 SDQM 0 0 SDQM 3 1 SDQM 2 1 SDQM 1 0 SDQM 0 0 SDQM 3 0 SDQM 2 0 SDQM 1 0 SDQM 0 0 01 SDQM 3 1 SDQM 2 1 SDQM 1 0 SDQM 0 1 10 SDQM 3 1 SDQM 2 0 SDQM 1 1 SDQM 0 1 SDQM 3 0 SDQM 2 0 SDQM 1 1 SDQM 0 1 1...

Page 794: ...t the required refresh rate based on the clock frequency used The refresh counter period is specified with the RDIV field in the SDRAM Refresh Rate Control register To allow Auto Refresh commands to e...

Page 795: ...been started any access to SDRAM address space regardless of the state of the EBxE bits generates an internal bus error and the access does not occur externally For more information see Error Detectio...

Page 796: ...peculative read accesses or prefetches in order to minimize the latency seen by L1 cache line fills The SDC stores the read data from these prefetches into a read buffer A cache line fill fetches 32 b...

Page 797: ...first word which is not in the read buffer and then starts this transfer from the SDRAM As long as there are enough words that hit in the read buffer to cover the latency of reading the remaining addr...

Page 798: ...buf fer are considered valid words All valid words which follow the critical word in a line wrapping manner are counted as read buffer hits For exam ple prefetch begins and stores words 7 0 1 2 and 3...

Page 799: ...or the SDRAM interface is as follows Precharge Closes all internal banks Activate Activates a page in the required SDRAM internal bank Load Mode Register Initializes the SDRAM operation parameters dur...

Page 800: ...s to be accessed falls in an open page in another external bank or to an external bank with no page open For page miss reads or writes only the external bank to be accessed by the read or write is pre...

Page 801: ...bus of the SDRAM as data input The power up sequence is initiated by writing 1 to the PSSE bit in the SDRAM Memory Global Control register EBIU_SDGCTL and then writing or read ing from any enabled ad...

Page 802: ...in the read buffer the SDC issues a Read command The SDC then speculatively issues Read commands if certain conditions are met For more information see Read Buffer Prefetch Operation on page 18 72 Th...

Page 803: ...arged Self Refresh mode is enabled by writing a 1 to the SRFS bit of the SDRAM Memory Global Control register EBIU_SDGCTL The SDRAM remains in Self Refresh mode for at least tRAS and until an internal...

Page 804: ...ut needs to insert addi tional commands with no effect the NOP command is given When the SDC is not accessing any SDRAM external banks the Command Inhibit command is given SDRAM Timing Specifications...

Page 805: ...e DMA or PCI read write accesses to 32 bit wide SDRAM For this example assume all cycles are SCLK cycles and the following SCLK frequency and SDRAM parameters are used SCLK frequency 133 MHz CAS laten...

Page 806: ...DMA Burst Write 4 words Write Page Hit 4 words 8 cycles DMA Burst Read 8 words Read Page Hit 8 words 13 cycles DMA Burst Write 8 words Write Page Hit 8 words 16 cycles Single Read Read Page Hit 1 wor...

Page 807: ...half word hit 8 words 8 cycles For N 5 to 0 N half word hit 8 words 14 N cycles If both EBUFE 1 and CL 11 For N 8 to 7 N half word hit 8 words 8 cycles For N 6 to 0 N half word hit 8 words 15 N cycles...

Page 808: ...cycles DMA Burst Write 4 words Write Page Hit 4 words 12 cycles DMA Burst Read 8 words Read Page Hit 8 words 21 cycles DMA Burst Write 8 words Write Page Hit 8 words 20 cycles Single Read Read Page H...

Page 809: ...AM Memory Global Control register is used all accesses take one extra cycle for each feature selected Accesses that hit in the Read Buffer follow these rules If either EBUFE 1 or CL 11 For N 16 to 13...

Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...

Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...

Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...

Page 813: ...of this manual In such cases a reference appears to the corresponding section of the text instead of repeating the discussion in this chapter Pin Descriptions Refer to ADSP BF535 Blackfin Embedded Pr...

Page 814: ...of methods These include executing from external 16 bit memory or booting from a ROM configured to load code from 8 bit FLASH memory or a serial ROM 8 bit or 16 bit address range For more information...

Page 815: ...pins During reset these pins act as multiplier selects when in multiplier mode and as pro grammable flags after reset This multiplexing influences system design as follows For systems selecting Bypass...

Page 816: ...e desired operating speed in the software Figure 19 1 External Clock Connections CLKIN 25 MHz Oscillator ADSP BF535 MSEL5 PF5 MSEL4 PF4 MSEL3 PF3 MSEL2 PF2 MSEL1 PF1 MSEL0 PF0 RESET MSEL6 PF6 DF PF7 V...

Page 817: ...r tMSS Setup for pin value before RESET deasserted The value must be held from this point until hold time completes tMSH Hold for pin value after RESET deasserted Configuring and Servicing Interrupts...

Page 818: ...it is no longer using the resource This signaling is accomplished via semaphores Semaphore coherency is guaranteed by using the Test and Set Byte Atomic instruction TESTSET The TESTSET instruction per...

Page 819: ...lt in unreliable behavior Example Code for Query Semaphore Listing 19 1 provides an example of a query semaphore that checks the availability of a shared resource Listing 19 1 Query Semaphore Query se...

Page 820: ...es For an explanation of prioritization between the various internal SBIU buses refer to Chip Bus Hierarchy on page 7 1 PCI Arbiter If the ADSP BF535 processor is intended for use as a PCI host in a g...

Page 821: ...t for deterministic access times of memories Figure 19 3 shows the glueless interface to 32 bit SRAM Note that this application requires the 32 bit datapath mode to be enabled for this bank of memory...

Page 822: ...case the ADSP BF535 processor s data bus drivers can potentially contend with those of the memory device addressed by the read The second case is back to back reads from two different memory spaces In...

Page 823: ...k Size MByte Bank Width Bits SDRAM Size Mbit Configuration Number of Chips Number of Column Address Pins 16 32 64 1M 16 4banks 2 8 32 32 64 2M 8 4banks 4 9 32 32 128 2M 16 4banks 2 9 64 32 64 4M 4 4ba...

Page 824: ...ps on the DIMM Most DIMMs can be interfaced to the ADSP BF535 processor gluelessly by using the SMS 3 0 bank selects the SDQM 3 0 data masks and careful connection of the data bus Divide the DIMM into...

Page 825: ...19 5 64 MB SDRAM System Example SCKE ADSP BF535 SWE SCAS SRAS SMSx 0 ADDR 19 ADDR 18 SA10 ADDR 13 11 2 WE CAS RAS SDRAM 1 CS A13 BS1 A 10 SCLK 0 SDQM 0 DATA 31 0 A12 BS0 A 11 9 0 CKE CLK DQM DQ 7 0 W...

Page 826: ...ocessor systems Point to Point Connections on Serial Ports Although the processor s serial ports may be operated at a slow rate the output drivers still have fast edge rates and for longer distances m...

Page 827: ...ch faster and reducing noise producing current spikes Signal run length inductance should also be minimized to reduce ring ing Extra care should be taken with certain signals such as external memory r...

Page 828: ...race length The ground planes must not be densely perforated with vias or traces as their effectiveness is reduced In addition there should be sev eral large tantalum capacitors on the board Designs c...

Page 829: ...tal Design A Handbook of Black Magic Johnson Gra ham Prentice Hall Inc ISBN 0 13 395724 1 Figure 19 7 Bypass Capacitor Placement CASE 1 BYPASS CAPACITORS ON NON COMPONENT BOTTOM SIDE OF BOARD BENEATH...

Page 830: ...red in state of the art high frequency digital circuit design It is an excellent source of information and practical ideas Topics covered in the book include High speed Properties of Logic Gates Measu...

Page 831: ...h the instruction bus and the data bus the Watchpoint Unit provides several mechanisms for examining program behavior After counting the number of times a particular address is matched the unit schedu...

Page 832: ...dress Control register WPIACTL Two Watchpoint Data Address registers WPDA 1 0 Two Watchpoint Data Address Count registers WPDACNT 1 0 The Watchpoint Data Address Control register WPDACTL Two operation...

Page 833: ...grouped together into one data address range watchpoint WPDA 1 0 The instruction and data count value registers must be loaded with one less than the number of times the watchpoint must match After th...

Page 834: ...g code with new code The watchpoint registers are used to trigger an exception at the start addresses of the earlier code The exception routine then vectors to the location in memory that contains the...

Page 835: ...and reset routines cannot be patched A write to the WPSTAT MMR clears all the sticky status bits The data value written is ignored Watchpoint Instruction Address Registers WPIAx When the Watchpoint Un...

Page 836: ...the watchpoint must match before triggering an event see Figure 20 2 Table 20 4 Watchpoint Instruction Address Register MMR Assignments Register Name Memory Mapped Address WPIA0 0xFFE0 7040 WPIA1 0xF...

Page 837: ...ter have no effect unless the WPPWR bit is set Figure 20 3 shows the upper half of the register and Figure 20 4 shows the lower half of the register For more information about the bits in this registe...

Page 838: ...tchpoint WPIA4 1 Enable instruction address watchpoint WPIA4 WPIAEN5 0 Disable instruction address watchpoint WPIA5 1 Enable instruction address watchpoint WPIA5 WPAND 0 Any enabled watchpoint trigger...

Page 839: ...MUSW0 EMUSW1 0 Match on WPIA1 causes an exception event 1 Match on WPIA1 causes an emulation event WPIREN23 0 Disable range comparison 1 Enable range comparison Start address WPIA2 End address WPIA3 W...

Page 840: ...ation events To enable the Data address watchpoints the WPPWR bit of the WPIACTL register must be set to 1 Table 20 6 Data Address Watchpoints Bit Names Description WPDACCx Determines whether the matc...

Page 841: ...es in these registers are decremented each time the address or the address bus matches a value in the WPDAx registers Load this WPDACNTx register with a value that is one less than the number of times...

Page 842: ...Watchpoint Data Address Count Value Register MMR Assignments Register Name Memory Mapped Address WPDACNT0 0xFFE0 7180 WPDACNT1 0xFFE0 7184 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X...

Page 843: ...on WPDA0 or on the WPDA0 to WPDA1 range 10 Match on read access only on WPDA0 or on the WPDA0 to WPDA1 range 11 Match on either read or write accesses on WPDA0 or on the WPDA0 to WPDA1 range WPDACC0 1...

Page 844: ...th The trace buffer can be enabled to cause an exception when full The exception service routine associated with the exception saves trace buffer entries to memory Thus the complete path of the progra...

Page 845: ...r DAG0 or DAG1 on WPDA1 WPDSRC1 1 0 00 Reserved 01 Match on write access only on WPDA0 or on the WPDA0 to WPDA1 range 10 Match on read access only on WPDA0 or on the WPDA0 to WPDA1 range 11 Match on e...

Page 846: ...mmended that TBUF be read in a non interruptible section of code Note if single level compression has occurred the LSB of the branch tar get address is set If two level compression has occurred the LS...

Page 847: ...X X 0 0 0 0 Trace Buffer Control Register TBUFCTL TBUFPWR 0 Trace buffer is off 1 Trace buffer is active TBUFEN 0 Trace buffer disabled 1 Trace buffer enabled TBUFOVF 0 Overflows are ignored 1 Trace b...

Page 848: ...utine the program flow discontinuities may be read from TBUF and stored in memory by using the follow ing code While TBUF is being read be sure to disable the trace buffer from recording new discontin...

Page 849: ...op1_start loop1_end lc0 p5 loop1_start r7 p3 read from TBUF loop1_end p4 r7 write to memory and increment p2 p4 pointer to the next available buf location is saved in the header of buf r7 7 p5 3 sp re...

Page 850: ...ce the unit is enabled individual count enable bits PFCENx take effect Use the PFCENx bits to enable or disable the performance monitors in User mode Supervisor mode or both Use the PEMUSWx bits to se...

Page 851: ...xception event 1 Count down of performance counter PFCNTR0 causes emulation event PFCEN0 1 0 00 Disable Performance Monitor 0 01 Enable Performance Monitor 0 in User mode only 10 Enable Performance Mo...

Page 852: ...0x01 L1 IC misses 0x02 L1 IC hits 0x04 L1 IC bank conflicts 0x05 L1 IC fill buffer hits 0x20 Loop0 iterations 0x21 Loop1 iterations 0x22 Loop buffer 0 invalidates because of branches jumps and similar...

Page 853: ...nk A load hits 0x65 Data Bank A store hits 0x66 Data Bank B load hits 0x67 Data Bank B store hits 0x68 L1 data memory hits 0x69 L1 data memory misses 0x6A Store buffer is full 0x6B Write buffer is ful...

Page 854: ...s are stored in CYCLES The most significant 32 bits are stored in CYCLES2 To ensure the correct cycle count a read from CYCLES must occur before reading from CYCLES2 In User mode these two registers m...

Page 855: ...bits Product Identification Registers The 32 bit Chip ID register CHIPID is a system MMR that contains the product identification and revision fields for the ADSP BF535 processor The 32 bit DSP Devic...

Page 856: ...ode CHIPID 31 28 silicon revision number CHIPID 27 12 part number 0x4000 CHIPID 11 1 Analog Devices Inc ID number 0xE5 drop the MSB parity and set MSBs to 0 no ID extension in accordance with the JTAG...

Page 857: ...hat provide visibility into the bus and control of it Additional information about the SBIU is avail able in Chip Bus Hierarchy on page 7 1 If a DMA channel does not behave as expected these two regis...

Page 858: ...s bit in DB_CCOMP If the interrupt is unmasked the hit also generates a Hardware Error interrupt to the core The source of the interrupt can be determined by reading the core MMR HWE Cause field in SE...

Page 859: ...s detected or the compare and count function is disabled A comparison match freezes the counter within two cycles of the assertion of CH DMA Bus Address Comparator Register DB_ACOMP Figure 20 18 shows...

Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...

Page 861: ...is document click a refer ence in the See Section column to jump to the additional information about the MMR L1 Data Memory Controller Registers Table A 1 lists the MMR assignments for the L1 Data Mem...

Page 862: ...ADDR7 DCPLB Address Registers DCPLB_ADDRx on page 6 69 0xFFE0 0120 DCPLB_ADDR8 DCPLB Address Registers DCPLB_ADDRx on page 6 69 0xFFE0 0124 DCPLB_ADDR9 DCPLB Address Registers DCPLB_ADDRx on page 6 69...

Page 863: ...DCPLB_DATA6 DCPLB Data Registers DCPLB_DATAx on page 6 65 0xFFE0 021C DCPLB_DATA7 DCPLB Data Registers DCPLB_DATAx on page 6 65 0xFFE0 0220 DCPLB_DATA8 DCPLB Data Registers DCPLB_DATAx on page 6 65 0...

Page 864: ...0xFFE0 0404 DTEST_DATA1 Data Test Data 1 Register DTEST_DATA1 on page 6 49 0xFFE0 0408 DTEST_DATA2 Data Test Data 0 Register DTEST_DATA0 on page 6 50 0xFFE0 040C DTEST_DATA3 Data Test Data 1 Register...

Page 865: ...DDR6 ICPLB Address Registers ICPLB_ADDRx on page 6 71 0xFFE0 111C ICPLB_ADDR7 ICPLB Address Registers ICPLB_ADDRx on page 6 71 0xFFE0 1120 ICPLB_ADDR8 ICPLB Address Registers ICPLB_ADDRx on page 6 71...

Page 866: ...ICPLB_DATA5 ICPLB Data Registers ICPLB_DATAx on page 6 67 0xFFE0 1218 ICPLB_DATA6 ICPLB Data Registers ICPLB_DATAx on page 6 67 0xFFE0 121C ICPLB_DATA7 ICPLB Data Registers ICPLB_DATAx on page 6 67 0...

Page 867: ...27 0XFFE0 1400 ITEST_DATA0 Instruction Test Data 0 Register ITEST_DATA0 on page 6 29 0XFFE0 1404 ITEST_DATA1 Instruction Test Data 1 Register ITEST_DATA1 on page 6 28 Table A 3 Interrupt Controller Re...

Page 868: ...on page 4 35 0xFFE0 202C EVT11 IVG11 Core Event Vector Table on page 4 35 0xFFE0 2030 EVT12 IVG12 Core Event Vector Table on page 4 35 0xFFE0 2034 EVT13 IVG13 Core Event Vector Table on page 4 35 0xFF...

Page 869: ...0 5000 0xFFE0 500C Table A 4 Core Timer Registers Memory Mapped Address Register Name See Section 0xFFE0 3000 TCNTL Core Timer Control Register TCNTL on page 16 22 0xFFE0 3004 TPERIOD Core Timer Perio...

Page 870: ...0 TBUFCTL Trace Buffer Control Register TBUFCTL on page 20 16 0xFFE0 6004 TBUFSTAT Trace Buffer Status Register TBUFSTAT on page 20 17 0xFFE0 6100 TBUF Trace Buffer Register TBUF on page 20 18 Table A...

Page 871: ...atchpoint Instruction Address Count Reg isters WPIACNTx on page 20 6 0xFFE0 7090 WPIACNT4 Watchpoint Instruction Address Count Reg isters WPIACNTx on page 20 6 0xFFE0 7094 WPIACNT5 Watchpoint Instruct...

Page 872: ...ance Monitor regis ters 0xFFE0 8000 0xFFE0 8104 Table A 8 Performance Monitor Registers Memory Mapped Address Register Name See Section 0xFFE0 8000 PFCTL Performance Monitor Control Register PFCTL on...

Page 873: ...MRs can only be accessed with 32 bit aligned memory operations A dedicated set of PCI registers reside at 0xEEFFFF00 0xEEFFFFFF All system MMR space that is not defined in this appendix is reserved fo...

Page 874: ...Address Register Name See Section 0xFFC0 0400 PLL_CTL PLL Control Register PLL_CTL on page 8 7 0xFFC0 0404 PLL_STAT PLL Status Register PLL_STAT on page 8 9 0xFFC0 0406 PLL_LOCKCNT PLL Lock Count Reg...

Page 875: ...ter Name See Section 0xFFC0 0C04 SIC_IAR0 System Interrupt Assignment Registers SIC_IARx on page 4 29 0xFFC0 0C08 SIC_IAR1 System Interrupt Assignment Registers SIC_IARx on page 4 29 0xFFC0 0C0C SIC_I...

Page 876: ...e Section 0xFFC0 1000 WDOG_CTL Watchdog Control Register WDOG_CTL on page 16 27 0xFFC0 1004 WDOG_CNT Watchdog Count Register WDOG_CNT on page 16 26 0xFFC0 1008 WDOG_STAT Watchdog Status Register WDOG_...

Page 877: ...UARTx Transmit Holding Regis ters UARTx_THR on page 12 5 0xFFC0 1800 UART0_RBR UARTx Receive Buffer Registers UARTx_RBR on page 12 6 0xFFC0 1800 UART0_DLL UARTx Divisor Latch Registers UARTx_DLL UARTx...

Page 878: ...rent Descriptor Pointer Registers UARTx_CURR_PTR_RX on page 12 19 0xFFC0 1A02 UART0_CONFIG_RX UARTx Receive DMA Configura tion Registers UARTx_CONFIG_RX on page 12 20 0xFFC0 1A04 UART0_START_ADDR_HI_R...

Page 879: ...FIG_TX UARTx Transmit DMA Configura tion Registers UARTx_CONFIG_TX on page 12 29 0xFFC0 1B04 UART0_START_ADDR_HI_TX UARTx Transmit DMA Start Address High Registers UARTx_START_ADDR_HI_TX on page 12 30...

Page 880: ...egisters Memory Mapped Address Register Name See Section 0xFFC0 1C00 UART1_THR UARTx Transmit Holding Regis ters UARTx_THR on page 12 5 0xFFC0 1C00 UART1_RBR UARTx Receive Buffer Registers UARTx_RBR o...

Page 881: ...Descriptor Pointer Registers UARTx_CURR_PTR_RX on page 12 19 0xFFC0 1E02 UART1_CONFIG_RX UARTx Receive DMA Configura tion Registers UARTx_CONFIG_RX on page 12 20 0xFFC0 1E04 UART1_START_ADDR_HI_RX UAR...

Page 882: ...CONFIG_TX UARTx Transmit DMA Configura tion Registers UARTx_CONFIG_TX on page 12 29 0xFFC0 1F04 UART1_START_ADDR_HI_TX UARTx Transmit DMA Start Address High Registers UARTx_START_ADDR_HI_TX on page 12...

Page 883: ...ion 0xFFC0 2000 TIMER0_STATUS Timer Status Registers TIMERx_STATUS on page 16 4 0xFFC0 2002 TIMER0_CONFIG Timer Configuration Registers TIMERx_CONFIG on page 16 7 0xFFC0 2004 TIMER0_COUNTER_LO Timer C...

Page 884: ...D_HI Timer Period Registers TIMERx_PERIOD on page 16 10 0xFFC0 201C TIMER1_WIDTH_LO Timer Width Registers TIMERx_WIDTH on page 16 11 0xFFC0 201E TIMER1_WIDTH_HI Timer Width Registers TIMERx_WIDTH on p...

Page 885: ...DIR Flag Direction Register FIO_DIR on page 15 2 0xFFC0 2404 FIO_FLAG_C Flag Set FIO_FLAG_S and Flag Clear FIO_FLAG_C Registers on page 15 2 0xFFC0 2406 FIO_FLAG_S Flag Set FIO_FLAG_S and Flag Clear F...

Page 886: ...on page 15 10 0xFFC0 2418 FIO_BOTH Flag Set on Both Edges Register FIO_BOTH on page 15 10 Table B 10 SPORT0 Controller Registers Memory Mapped Address Register Name See Section 0xFFC0 2800 SPORT0_TX_...

Page 887: ...nd Receive SPORTx_RFSDIV Frame Sync Divider Registers on page 11 22 0xFFC0 2810 SPORT0_STAT SPORTx Status SPORTx_STAT Registers on page 11 23 0xFFC0 2812 SPORT0_MTCS0 SPORTx Multichannel Transmit Sele...

Page 888: ...ve Select SPORTx_MRCSx Registers on page 11 27 0xFFC0 2826 SPORT0_MRCS2 SPORTx Multichannel Receive Select SPORTx_MRCSx Registers on page 11 27 0xFFC0 2828 SPORT0_MRCS3 SPORTx Multichannel Receive Sel...

Page 889: ...isters on page 11 31 0xFFC0 2A04 SPORT0_START_ADDR_HI_RX SPORTx Receive DMA Start Address High SPORTx_START_ADDR_HI_RX Registers on page 11 34 0xFFC0 2A06 SPORT0_START_ADDR_LO_RX SPORTx Receive DMA St...

Page 890: ...ORTx_START_ADDR_HI_TX Registers on page 11 43 0xFFC0 2B06 SPORT0_START_ADDR_LO_TX SPORTx Transmit DMA Start Address Low SPORTx_START_ADDR_LO_TX Registers on page 11 44 0xFFC0 2B08 SPORT0_COUNT_TX SPOR...

Page 891: ...CONFIG SPORTx_RX_CONFIG on page 11 9 0xFFC0 2C04 SPORT1_TX SPORTx Transmit SPORTx_TX Registers on page 11 17 0xFFC0 2C06 SPORT1_RX SPORTx Receive SPORTx_RX Registers on page 11 19 0xFFC0 2C08 SPORT1_T...

Page 892: ...RTx_MTCSx Registers on page 11 25 0xFFC0 2C1A SPORT1_MTCS4 SPORTx Multichannel Transmit Select SPORTx_MTCSx Registers on page 11 25 0xFFC0 2C1C SPORT1_MTCS5 SPORTx Multichannel Transmit Select SPORTx_...

Page 893: ...SPORTx Multichannel Receive Select SPORTx_MRCSx Registers on page 11 27 0xFFC0 2C30 SPORT1_MRCS7 SPORTx Multichannel Receive Select SPORTx_MRCSx Registers on page 11 27 0xFFC0 2C32 SPORT1_MCMC1 SPORTx...

Page 894: ...EXT_DESCR_RX Registers on page 11 36 0xFFC0 2E0C SPORT1_DESCR_RDY_RX SPORTx Receive DMA Descriptor Ready SPORTx_DESCR_RDY_RX Registers on page 11 37 0xFFC0 2E0E SPORT1_IRQSTAT_RX SPORTx Receive DMA IR...

Page 895: ...T1_NEXT_DESCR_TX SPORTx Transmit DMA Next Descriptor Pointer SPORTx_NEXT_DESCR_TX Registers on page 11 45 0xFFC0 2F0C SPORT1_DESCR_RDY_TX SPORTx Transmit DMA Descriptor Ready SPORTx_DESCR_RDY_TX Regis...

Page 896: ...on Register SPIx_CONFIG on page 10 21 0xFFC0 3204 SPI0_START_ADDR_HI SPIx DMA Start Address High Register SPIx_START_ADDR_HI and SPIx DMA Start Address Low Register SPIx_START_ADDR_LO on page 10 22 0x...

Page 897: ...on page 10 17 0xFFC0 3408 SPI1_RDBR SPIx Receive Data Buffer Register SPIx_RDBR on page 10 18 0xFFC0 340A SPI1_BAUD SPIx Baud Rate Register SPIx_BAUD on page 10 7 0xFFC0 340C SPI1_SHADOW SPIx RDBR Sha...

Page 898: ...PIx DMA Interrupt Register SPIx_DMA_INT on page 10 26 Table B 14 Memory DMA Controller Registers Memory Mapped Address Register Name See Section 0xFFC0 3800 MDD_DCP Destination Memory DMA Current Desc...

Page 899: ...uration Regis ter MDS_DCFG on page 9 39 0xFFC0 3904 MDS_DSAH Source Memory DMA Start Address Regis ters MDS_DSAH MDS_DSAL on page 9 41 0xFFC0 3906 MDS_DSAL Source Memory DMA Start Address Regis ters M...

Page 900: ...rs Memory Mapped Address Register Name See Section 0xFFC0 3C00 EBIU_AMGCTL Asynchronous Memory Global Control Reg ister EBIU_AMGCTL on page 18 10 0xFFC0 3C04 EBIU_AMBCTL0 Asynchronous Memory Bank Cont...

Page 901: ...e I O BAR Mask Register PCI_DIBARM on page 13 27 0xEEFF FF08 PCI_CFG_DIC PCI Configuration Device ID Register PCI_CFG_DIC on page 13 29 0xEEFF FF0C PCI_CFG_VIC PCI Configuration Vendor ID Register PCI...

Page 902: ...figuration Subsystem ID Register PCI_CFG_SID on page 13 40 0xEEFF FF3C PCI_CFG_SVID PCI Configuration Subsystem Vendor ID Register PCI_CFG_SVID on page 13 40 0xEEFF FF40 PCI_CFG_MAXL PCI Configuration...

Page 903: ...Configuration Into UDC Core Register USBD_EPBUF on page 14 18 0xFFC0 4408 USBD_STAT USBD Module Status Register USBD_STAT on page 14 19 0xFFC0 440A USBD_CTRL USBD Module Configuration and Control Regi...

Page 904: ...Endpoint x Interrupt Registers USBD_INTRx on page 14 27 0xFFC0 448C USBD_MASK1 USB Endpoint x Mask Registers USBD_MASKx on page 14 29 0xFFC0 448E USBD_EPCFG1 USB Endpoint x Control Registers USBD_EPC...

Page 905: ...Endpoint x Interrupt Registers USBD_INTRx on page 14 27 0xFFC0 44AA USBD_MASK4 USB Endpoint x Mask Registers USBD_MASKx on page 14 29 0xFFC0 44AC USBD_EPCFG4 USB Endpoint x Control Registers USBD_EPCF...

Page 906: ...ddress Offset Registers USBD_EPADRx on page 14 33 0xFFC0 44C4 USBD_EPLEN6 USB Endpoint x Buffer Length Registers USBD_EPLENx on page 14 34 0xFFC0 44C6 USBD_INTR7 USB Endpoint x Interrupt Registers USB...

Page 907: ...4880 DMA_DBP DMA Descriptor Base Pointer Register DMA_DBP on page 9 24 0xFFC0 4884 DB_ACOMP DMA Bus Address Comparator Register DB_ACOMP on page 20 29 0xFFC0 4888 DB_CCOMP DMA Bus Control Comparator R...

Page 908: ...SDRAM Controller External Bus Interface Unit B 36 ADSP BF535 Blackfin Processor Hardware Reference...

Page 909: ...the component can respond to a mini mum set of instructions designed to help test printed circuit boards The standard defines test logic that can be included in an integrated cir cuit to provide stand...

Page 910: ...registers defined by the JTAG standard The TAP controller is a synchronous 16 state finite state machine con trolled by the TCK and TMS pins Transitions to the various states in the diagram occur on...

Page 911: ...ronously asserted An external system reset does not affect the state of the TAP con troller nor does the state of the TAP controller affect an external system reset Figure C 1 TAP Controller State Dia...

Page 912: ...tructions are reserved for the manu facturer s use The Binary Decode column of Table C 2 shows the decode for the public instructions The Register column shows the serial scan paths Table C 2 Decode f...

Page 913: ...r the paths shown in Table C 2 EMUPC_SCAN 10110 BYPASS 11111 Bypass Figure C 2 Serial Scan Paths Table C 2 Decode for Public JTAG Scan Instructions Cont d Instruction Name Binary Decode 01234 Register...

Page 914: ...the boundary outputs are over driven or signals are received on the boundary inputs make sure that nothing else drives data on the ADSP BF535 processor s out put pins SAMPLE PRELOAD Binary Code 10000...

Page 915: ...er the JTAG standard CHIPID is selected by default during the Test Logic Reset controller state BYPASS Binary Code 11111 The BYPASS instruction selects the BYPASS register to be connected to TDI and T...

Page 916: ...h The posi tions are numbered from 0 to 468 Bit 0 is the first bit output closest to TDO and bit 468 is the last bit output closest to TDI Table C 3 Scan Path Position Definitions Position Type Signal...

Page 917: ...O TMR 0 27 OE TMR 0 OE 28 I TMR 0 29 O ADDR 2 30 OE ADDR 2 OE 31 O ADDR 3 32 OE ADDR 3 OE 33 O ADDR 4 34 OE ADDR 4 OE 35 O ADDR 5 36 OE ADDR 5 OE 37 O ADDR 6 38 OE ADDR 6 OE 39 O ADDR 7 40 OE ADDR 7 O...

Page 918: ...2 OE ADDR 13 OE 53 O ADDR 14 54 OE ADDR 14 OE 55 O ADDR 15 56 OE ADDR 15 OE 57 O ADDR 16 58 OE ADDR 16 OE 59 O ADDR 17 60 OE ADDR 17 OE 61 O ADDR 18 62 OE ADDR 18 OE 63 O ADDR 19 64 OE ADDR 19 OE 65 O...

Page 919: ...78 OE ABE_SDQM 0 OE 79 O ABE_SDQM 1 80 OE ABE_SDQM 1 OE 81 O ABE_SDQM 2 82 OE ABE_SDQM 2 OE 83 O ABE_SDQM 3 84 OE ABE_SDQM 3 OE 85 O AMS 0 86 OE AMS 0 OE 87 O AMS 1 88 OE AMS 1 OE 89 O AMS 2 90 OE AM...

Page 920: ...3 O SCKE 104 OE SCKE OE 105 O SA10 106 OE SA10 OE 107 O SRAS 108 OE SRAS OE 109 O SWE 110 OE SWE OE 111 O SMS 3 112 OE SMS 3 OE 113 O SMS 2 114 OE SMS 2 OE 115 O SMS 1 116 OE SMS 1 OE 117 O SMS 0 118...

Page 921: ...0 I DATA 2 131 O DATA 3 132 OE DATA 3 OE 133 I DATA 3 134 O DATA 4 135 OE DATA 4 OE 136 I DATA 4 137 O DATA 5 138 OE DATA 5 OE 139 I DATA 5 140 O DATA 6 141 OE DATA 6 OE 142 I DATA 6 143 O DATA 7 144...

Page 922: ...E DATA 11 OE 157 I DATA 11 158 O DATA 12 159 OE DATA 12 OE 160 I DATA 12 161 O DATA 13 162 OE DATA 13 OE 163 I DATA 13 164 O DATA 14 165 OE DATA 14 OE 166 I DATA 14 167 O DATA 15 168 OE DATA 15 OE 169...

Page 923: ...20 183 OE DATA 20 OE 184 I DATA 20 185 O DATA 21 186 OE DATA 21 OE 187 I DATA 21 188 O DATA 22 189 OE DATA 22 OE 190 I DATA 22 191 O DATA 23 192 OE DATA 23 OE 193 I DATA 23 194 O DATA 24 195 OE DATA 2...

Page 924: ...E DATA 28 OE 208 I DATA 28 209 O DATA 29 210 OE DATA 29 OE 211 I DATA 29 212 O DATA 30 213 OE DATA 30 OE 214 I DATA 30 215 O DATA 31 216 OE DATA 31 OE 217 I DATA 31 218 O PF 0 219 OE PF 0 OE 220 I PF...

Page 925: ...O PF 5 234 OE PF 5 OE 235 I PF 5 236 O PF 6 237 OE PF 6 OE 238 I PF 6 239 O PF 7 240 OE PF 7 OE 241 I PF 7 242 O PF 8 243 OE PF 8 OE 244 I PF 8 245 O PF 9 246 OE PF 9 OE 247 I PF 9 248 O PF 10 249 OE...

Page 926: ...E 259 I PF 13 260 O PF 14 261 OE PF 14 OE 262 I PF 14 263 O PF 15 264 OE PF 15 OE 265 I PF 15 266 O RSCLK0 267 OE RSCLK0 OE 268 I RSCLK0 269 O RFS0 270 OE RFS0 OE 271 I RFS0 272 I DR0 273 O TSCLK0 274...

Page 927: ...OE RFS1 OE 286 I RFS1 287 I DR1 288 O TSCLK1 289 OE TSCLK1 OE 290 I TSCLK1 291 O TFS1 292 OE TFS1 OE 293 I TFS1 294 O DT1 295 OE DT1 OE 296 O MOSI0 297 OE MOSI0 OE 298 I MOSI0 299 O MISO0 300 OE MISO...

Page 928: ...314 O PCI_AD 31 315 OE PCI_AD 31 OE 316 I PCI_AD 31 317 O PCI_AD 30 318 OE PCI_AD 30 OE 319 I PCI_AD 30 320 O PCI_AD 29 321 OE PCI_AD 29 OE 322 I PCI_AD 29 323 O PCI_AD 28 324 OE PCI_AD 28 OE 325 I PC...

Page 929: ...I_AD 23 OE 340 I PCI_AD 23 341 O PCI_AD 22 342 OE PCI_AD 22 OE 343 I PCI_AD 22 344 O PCI_AD 21 345 OE PCI_AD 21 OE 346 I PCI_AD 21 347 O PCI_AD 20 348 OE PCI_AD 20 OE 349 I PCI_AD 20 350 O PCI_AD 19 3...

Page 930: ...5 365 O PCI_AD 14 366 OE PCI_AD 14 OE 367 I PCI_AD 14 368 O PCI_AD 13 369 OE PCI_AD 13 OE 370 I PCI_AD 13 371 O PCI_AD 12 372 OE PCI_AD 12 OE 373 I PCI_AD 12 374 O PCI_AD 11 375 OE PCI_AD 11 OE 376 I...

Page 931: ...391 I PCI_AD 6 392 O PCI_AD 5 393 OE PCI_AD 5 OE 394 I PCI_AD 5 395 O PCI_AD 4 396 OE PCI_AD 4 OE 397 I PCI_AD 4 398 O PCI_AD 3 399 OE PCI_AD 3 OE 400 I PCI_AD 3 401 O PCI_AD 2 402 OE PCI_AD 2 OE 403...

Page 932: ...I_CBE 2 417 OE PCI_CBE 2 OE 418 I PCI_CBE 2 419 O PCI_CBE 3 420 OE PCI_CBE 3 OE 421 I PCI_CBE 3 422 O PCI_IRDY 423 OE PCI_IRDY OE 424 I PCI_IRDY 425 O PCI_RST 426 OE PCI_RST OE 427 I PCI_RST 428 O PCI...

Page 933: ...CI_STOP OE 443 I PCI_STOP 444 O PCI_PERR 445 OE PCI_PERR OE 446 I PCI_PERR 447 O PCI_PAR 448 OE PCI_PAR OE 449 I PCI_PAR 450 O PCI_SERR 451 OE PCI_SERR OE 452 I PCI_SERR 453 I PCI_LOCK 454 I PCI_CLK 4...

Page 934: ...re C 26 ADSP BF535 Blackfin Processor Hardware Reference 462 I BMODE 1 463 I BMODE 2 464 O SLEEP 465 OE SLEEP OE 466 I BYPASS 467 O EMU 468 OE EMU OE Table C 3 Scan Path Position Definitions Cont d Po...

Page 935: ...is con tained in the bits Therefore the value of an unsigned integer is interpreted in the usual binary sense The least significant words of multi ple precision numbers are treated as unsigned numbers...

Page 936: ...sumed radix point lies to the left of the 3 LSBs and the bits have the weights indicated The native formats for the Blackfin family are a signed fractional 1 M for mat and an unsigned fractional 0 N f...

Page 937: ...cond is the number of bits to the right of the radix point For example 16 0 format is an integer format all bits lie to the left of the radix point The format in Figure D 2 is 13 3 Figure D 2 Example...

Page 938: ...01 In Decimal 1 15 1 15 0 999969482421875 1 0 0 000030517578125 2 14 2 14 1 999938964843750 2 0 0 000061035156250 3 13 3 13 3 999877929687500 4 0 0 000122070312500 4 12 4 12 7 999755859375000 8 0 0 00...

Page 939: ...3 3 numbers is a 26 6 number The product of two 1 15 numbers is a 2 30 number Fractional Mode and Integer Mode A product of 2 two s complement numbers has two sign bits Since one of these bits is redu...

Page 940: ...range of a floating point format without the overhead needed to do floating point arithmetic Some additional pro gramming is required to maintain a block floating point format however A floating poin...

Page 941: ...e usage and syntax of these instructions Initially the value of SB is 2 corresponding to the 2 guard bits During processing each resulting data value is inspected by the EXPADJ instruction which count...

Page 942: ...1 1 1 0x3FFF 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x07FF 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 Shift right to restore guard bits Sign Bit 2 Guard Bits 0x0FFF 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0x1FFF 0 0 0 1 1 1...

Page 943: ...ost accesses of the processor that occur intermittently rather than as a steady stream Bank Activate command The Bank Activate command causes the SDRAM to open an internal bank specified by the bank a...

Page 944: ...after a software reset burst length The burst length determines the number of words that the SDRAM device stores or delivers after detecting a single write or read command respec tively The burst len...

Page 945: ...unit of memory that is transferred to from the next level of memory from to a cache as a result of a cache miss cache hit A memory access that is satisfied by a valid present entry in the cache cache...

Page 946: ...he SDC can support CAS latency of 2 or 3 clock cycles The selected CAS latency value must be programmed into the SDRAM Memory Global Control register EBIU_SDGCTL before the SDRAM power up sequence See...

Page 947: ...sm The CEC works with the System Interrupt Controller SIC to prioritize and control all system interrupts The CEC handles general purpose inter rupts and interrupts routed from the SIC CPLB See Cachea...

Page 948: ...When successive DMA sequences are needed the descriptor blocks are chained together so that the completion of one DMA sequence autoinitiates and starts the next sequence descriptor loading DMA The pr...

Page 949: ...ag indicating whether the data in the data cache line has been changed since it was copied from the source memory and therefore needs to be updated in that source memory DMA See Direct Memory Access D...

Page 950: ...ycles For 16 bit wide SDRAM only SDQM 1 0 are needed for byte masking DRAM Dynamic Random Access Memory A type of semiconductor memory in which the data are stored as electrical charges in an array of...

Page 951: ...ry contains a vector address for an interrupt service routine ISR When an event occurs instruction fetch starts at the address location in the corresponding EVT entry See ISR exclusive clean The state...

Page 952: ...of bytes in a multibyte number The processor uses big endian format moves data starting with most significant bit and finish ing with least significant bit in almost all instances The two exceptions...

Page 953: ...from which items are taken out in the same order they were put in Also known as a shelf from the analogy of pushing items onto one end of a shelf so that they fall off the other flag update A refresh...

Page 954: ...r get a data word and an instruction simultaneously HLL High Level Language A programming language that provides some level of abstraction above assembly language often using English like statements w...

Page 955: ...e some direct non DMA access to internal memory and I O memory I O processor register One of the control status or data buffer registers of the processor s on chip I O processor input clock Device tha...

Page 956: ...Association A nonprofit trade association that established standards for ensuring the quality and interoperability of devices using the infrared spectrum isochronous Processes where data must be deli...

Page 957: ...flow to another part of program memory latency The overhead time used to find the correct place for memory access and preparing to access it Least Recently Used algorithm Replacement algorithm used by...

Page 958: ...with the stack of plates in a cafeteria in which the most recent plate placed on the stack is on top and thus will be the next plate removed See Stack little endian The native data store format of the...

Page 959: ...ch allows specification of the SDRAM device s functionality After power up and before executing a read or write to the SDRAM memory space the appli cation must trigger the SDC to write the SDRAM s mod...

Page 960: ...ry locations in the processor that can be addressed with just a few bits memory mapped registers must be addressed in the same way as other memory locations and the speed of MMR accesses is limited to...

Page 961: ...n which a one 1 is represented by a change in the signal and a zero 0 by no change there is no return to a reference zero voltage between encoded bits This method eliminates the need for a clock signa...

Page 962: ...age size 2 CAW 1 where CAW is the column address width of the SDRAM plus 1 because the SDRAM bank is 16 bits wide 1 address bit 2 bytes PC Program Counter A register that contains the address of the n...

Page 963: ...ces a full speed master clock from a lower frequency input clock signal PIO Programmed Input Output A way of moving data between system devices and memory in which all data must pass through the proce...

Page 964: ...nagement unit MMU to a DRAM device to indicate that the row address lines are valid Real Time Clock RTC A component that generates timing pulses for the digital watch features of the ADSP BF535 proces...

Page 965: ...s represented by a change from the high volt age level to the low voltage level A return to a reference zero voltage is made between encoded bits saturation ALU saturation mode A state in which all po...

Page 966: ...s information can be read to determine the type size and timing parameters of installed DIMMs at boot time One of the SPI or SPORT peripherals of the ADSP BF535 processor can be used to interface to t...

Page 967: ...ine placement to a number of sets or Ways shifter A computational unit that completes logical and arithmetic shifts on 16 bit operands and derives exponents SIC System Interrupt Controller Part of the...

Page 968: ...n first out LIFO order When a data item is added to the stack it is said to be pushed when a data item is removed from the stack it is popped Static Random Access Memory SRAM Very fast memory that doe...

Page 969: ...interrupt inputs of the CIC subroutine A self contained section of a program with an entry point and an exit that usually performs a single task The main program flow branches to a subroutine when it...

Page 970: ...rt of the first Read or Write command The TRCD bit field in the SDRAM Memory Global Control register EBIU_SDGCTL is 3 bits wide and can be pro grammed to be from 1 to 7 clock cycles long tWR Required...

Page 971: ...lf Refresh mode and issuing the Auto Refresh command This delay is not directly programmable and is assumed to be equal to tRC The tRC delay must be satisfied by program ming the tRAS and tRP fields t...

Page 972: ...on with the USB host using the USB serial link and presents data and command transactions to the application Universal Serial Bus USB A module that handles USB protocol requirements It also contains h...

Page 973: ...Von Neumann architecture The architecture used by most non DSP microprocessors This architec ture uses a single address and data bus for memory access For John von Neumann 1903 1957 a Hungarian born...

Page 974: ...written only to the cache line The modified cache line is written to source mem ory only when it is replaced write through A cache write policy also known as store through The write data is writ ten t...

Page 975: ...fy Data Address Generators addressing modes 5 15 address tag compare operation 6 19 ADSP 21535 boot modes 1 24 clock signals 1 23 instruction set 1 24 operating modes 1 22 ADSP 21535 bus hierarchy fig...

Page 976: ...tency 7 13 PAB 7 8 SPORTs and USB 14 3 USB DMA channel 14 3 ARDY 18 13 18 26 arithmetic formats summary 2 15 to 2 16 operations 2 24 shifts 2 1 Arithmetic Logic Unit ALU 2 1 2 24 to 2 32 arithmetic 2...

Page 977: ...ion 2 1 bit set 2 48 bit test 2 48 bit toggle 2 48 bit reversed addressing 5 1 5 9 bit stream on the TxD pin figure 12 2 bitstuff violations 14 61 Blackfin DSP family instruction set 1 24 I O memory s...

Page 978: ...m PCI 13 7 buses concurrent operations 7 6 hierarchy 7 1 on chip 7 1 PCI AD 13 6 peripheral 7 8 buses continued USB master slave 14 3 See also DAB EAB EMB PAB bus loading 14 4 bus operation ordering P...

Page 979: ...on registers 11 66 CH Compare Hit bit 20 28 CHIPID Chip ID register 20 26 C 4 C 7 Chip ID register CHIPID 20 26 C 4 C 7 circuit board testing C 1 C 6 circular buffer addressing 5 6 registers 5 6 wrap...

Page 980: ...ions 11 67 Compare Hit CH bit 20 28 computation instructions 2 1 status 2 22 concurrent bus operations 7 6 conditional JUMP instruction 4 10 move instruction 4 13 conditional branches 4 13 4 14 6 81 b...

Page 981: ...Core Only Software reset 3 13 3 17 3 18 Core Timer 4 46 Core Timer Control register TCNTL 16 22 Core Timer Count register TCOUNT 16 23 Core Timer Period register TPERIOD 16 24 Core Timer Scale regist...

Page 982: ...rt operations 11 69 data packet shortened USB 14 48 Data Receive serial DRx pins 11 3 11 4 Data Register File 2 5 data registers 2 5 3 4 data sampling serial 11 57 data store format 6 3 Data Test Comm...

Page 983: ...register MDD_DI 9 38 Destination Memory DMA Next Descriptor Pointer register MDD_DND 9 36 Destination Memory DMA Start Address High register MDD_DSAH 9 35 Destination Memory DMA Start Address Low reg...

Page 984: ...ter register 9 26 DMA_DBP DMA Descriptor Base Pointer register 9 24 DMA Descriptor Base Pointer register DMA_DBP 9 24 DMA Descriptor Ready register 9 25 DMA_ERROR interrupt 14 41 DMA IRQ Status regist...

Page 985: ...gister 18 10 EBIU External Bus Interface Unit as slave 18 4 asynchronous interfaces supported 18 1 block diagram 18 3 bus error 18 9 clock 18 1 EBIU External Bus Interface Unit continued clocking 8 1...

Page 986: ...event definition 4 18 exception 4 38 latency in servicing 4 58 nested 4 33 Event Controller 3 1 4 17 MMRs 4 31 Sequencer 4 3 Event Controller Registers 4 31 event handling 1 10 event monitor 20 22 eve...

Page 987: ...ddress 4 2 FFT calculations 5 9 FIFO 18 1 PCI transaction 13 7 figure Core Interrupt Latch Register 4 33 figure Core Interrupt Mask Register 4 32 figure Core Interrupt Pending Register 4 33 figure Min...

Page 988: ...FIO_MASKB_S 15 5 Flag Interrupt Mask registers 15 5 Flag Interrupt Sensitivity register FIO_EDGE 15 10 Flag Polarity register FIO_POLAR 15 9 flags PCI status register 13 22 programmable 15 1 Transmit...

Page 989: ...13 Harvard architecture 6 9 header type PCI 13 36 heavy clock load and SDRAM 18 44 hierarchical memory structure 1 5 hold for EBIU asynchronous memory controller 18 12 host mode PCI inbound transactio...

Page 990: ...Cacheability Protection Lookaside Buffer Data registers ICPLB_DATAx 6 67 Instruction Decode DEC 4 7 Instruction Fetch 1 IF1 4 7 Instruction Fetch 2 IF2 4 7 Instruction Fetch Core I bus 7 3 instruction...

Page 991: ...18 4 46 generated by peripheral 4 20 global enabling and disabling 4 34 handling instructions in pipeline 4 54 hardware error 4 44 masking USB 14 30 multiple sources 4 21 nested 4 33 interrupts conti...

Page 992: ...9 IVHW interrupt 4 44 IVTMR core event 4 19 J JTAG port 3 17 standard 20 26 C 1 C 2 C 4 jump 4 1 JUMP instructions 4 9 conditional 4 10 range 4 11 L L1 interface System L1 bus 7 4 L1 memory See Level...

Page 993: ...RAM 7 5 7 7 little endian data ordering 6 3 load speculative execution 6 81 Load Mode Register 18 77 Load Mode Register command 18 77 load operation 6 77 load ordering 6 79 locked transfers DMA 7 12 l...

Page 994: ...terrupt register 9 38 MDD_DND Destination Memory DMA Next Descriptor Pointer register 9 36 MDD_DSAH Destination Memory DMA Start Address High register 9 35 MDD_DSAL Destination Memory DMA Start Addres...

Page 995: ...p PCI 13 4 memory mapped registers MMRs 6 84 to 6 85 PCI on EAB 13 26 memory reference exception for 4 38 microcontroller load store instructions 5 5 minimal clock load and SDRAM 18 44 miss read buffe...

Page 996: ...L field 8 3 multiply without accumulate 2 40 muxing SDRAM addressing 18 60 N nested interrupt 4 33 logging 4 52 Nested Interrupt Handling figure 4 50 Nested Interrupts 4 48 nested ISR example Epilog c...

Page 997: ...er 14 43 overview 4 1 7 1 11 1 P PAB Agents Masters Slaves 7 9 PAB Peripheral Access bus 7 8 and EBIU 18 4 and USB 14 10 arbitration 7 8 bus agents masters slaves 7 9 clocking 8 1 performance 7 8 pack...

Page 998: ...resources 13 12 outbound configuration 13 15 overview 13 1 parity error 13 8 power domains 13 45 power savings 8 24 programming model 13 18 PCI continued reflected wave switching 13 44 requirements e...

Page 999: ...ister PCI_CFG_CMD 13 32 PCI Configuration Device ID register PCI_CFG_DIC 13 29 PCI Configuration Header Type register PCI_CFG_HT 13 36 PCI Configuration Interrupt Line register PCI_CFG_IL 13 43 PCI Co...

Page 1000: ...BAP PCI Inbound Memory Base Address register 13 25 PCI to PCI bridge 13 15 PC Relative Indirect Branch and Call 4 12 PDWN bit 8 8 performance DAB 7 11 EAB 7 15 EAB estimates table 7 15 EMB 7 18 perfor...

Page 1001: ...code example Active mode to Full On mode 8 21 code example changing clock multiplier 8 21 PLL continued code example Full On mode to Active mode 8 21 configuration 8 2 control bits 8 15 Deep Sleep mo...

Page 1002: ...ing 5 1 5 4 5 7 5 11 post modify buffer access 5 7 power dissipation 8 23 power domains 8 23 PCI 13 45 power down warning as NMI 4 38 power management 8 1 to 8 27 power sequencing 13 45 power up 18 32...

Page 1003: ...for value 18 55 field 18 54 18 70 read access for EBIU asynchronous memory controller 18 12 read buffer miss 18 73 read buffer operation 18 72 read transfers to SDRAM banks 18 68 Read Write command 1...

Page 1004: ...n 4 10 return address 4 2 4 9 Return Address registers 4 4 return instructions 4 10 RETx register 3 5 revision ID PCI 13 34 RND_MOD bit 2 18 2 20 ROM 1 8 1 12 18 1 rounding biased 2 18 2 20 convergent...

Page 1005: ...bit 18 40 18 43 SDC 18 28 18 53 commands 18 75 EBIU block diagram 18 3 glueless interface features 18 28 operation 18 70 SDC continued set up 18 70 SDC Commands 18 75 SDC Configuration 18 70 SDC Opera...

Page 1006: ...in User mode 3 4 Sequencer Related Registers 4 3 Sequencer Status Register SEQSTAT 4 4 Sequencer Status register SEQSTAT 4 4 Serial communications 12 2 serial communications 12 2 Serial Peripheral Int...

Page 1007: ...ons 2 25 single master multiple slave SPI configuration diagram 10 15 Single Step exception 4 43 slaves DAB 7 14 EAB 7 17 EBIU 18 4 EMB 7 18 PAB 7 9 slave select SPI 10 11 Sleep mode 1 23 SNEN bit 4 5...

Page 1008: ...DMA Descriptor Ready registers 10 25 10 28 SPIx DMA Configuration registers SPIx_CONFIG 10 21 10 27 SPIx DMA Count registers SPIx_COUNT 10 23 10 27 SPIx DMA Current Descriptor Pointer registers SPIx_C...

Page 1009: ...ext descriptor pointer SPORTx_NEXT_DESC_RX registers 11 37 SPORT receive DMA start address high SPORTx_START_ADDR_HI_RX registers 11 35 SPORT receive DMA start address low SPORTx_START_ADDR_LO_RX regi...

Page 1010: ...SPORTx_MCMCx SPORTx Multichannel Configuration registers 11 30 11 31 SPORTx_MRCSx SPORTx Multichannel Receive Select registers 11 28 SPORTx_MTCSx SPORTx Multichannel Transmit Select registers 11 26 1...

Page 1011: ...Address Low registers 11 36 SPORTx_START_ADDR_LO_TX SPORTx Transmit DMA Start Address Low registers 11 45 SPORTx_STAT SPORTx Status registers 11 24 SPORTx Status registers SPORTx_STAT 11 24 SPORTx_TFS...

Page 1012: ...register EBIU 18 8 status registers accessible in User mode 3 4 STI See Enable Interrupts STI STOPCK field 8 8 stopwatch function RTC 17 2 stopwatch interrupt 17 8 store operation 6 77 store ordering...

Page 1013: ...1 bus 7 4 system overview 7 5 System Peripheral Interrupts 4 22 System Reset Configuration register SYSCR 3 14 System Software reset 3 12 3 14 system stack recommendation for allocating 4 58 T tAA 18...

Page 1014: ...imers 1 17 general purpose 1 2 UART 12 1 watchdog 1 2 1 16 Timer Status registers TIMERx_STATUS 16 2 16 3 16 4 Timer Width registers TIMERx_WIDTH 16 3 16 4 16 11 TIMERx_CONFIG TimerConfiguration regis...

Page 1015: ...bit 11 10 11 18 11 61 tRAS 18 34 TRAS bits 18 40 18 48 tRC 18 35 tRCD 18 35 TRCD bits 18 40 tRFC 18 36 tRP 18 35 TRP bits 18 40 18 48 TSCALE Core Timer Scale register 16 24 tWR 18 35 TWR bits 18 40 18...

Page 1016: ...atus registers 12 35 UARTx_LCR UARTx Line Control registers 12 3 UARTx Line Control registers UARTx_LCR 12 3 UARTx line control registers UARTx_LCR 12 3 UARTx Line Status Registers UARTx_LSR 12 4 UART...

Page 1017: ...ART_ADDR_LO_RX 12 23 UARTx Receive DMA Start Address Low registers UARTx_START_ADDR_LO_RX 12 23 UARTx Receive DMA Transfer Count Registers UARTx_COUNT_RX 12 24 UARTx Scratch Registers UARTx_SCR 12 15...

Page 1018: ...5 UDC 14 1 clock control 14 7 clocking 14 13 UDC continued configuration 14 44 device software 14 12 module in USB 14 6 UDC Endpoint Buffer register 14 35 unbiased rounding 2 18 unconditional branche...

Page 1019: ...14 memory allocation for endpoints 14 4 memory buffer offset 14 33 Memory Interface module 14 8 packet request 14 20 USB continued programming endpoint configuration registers 14 47 protocol 14 2 refe...

Page 1020: ...eld 14 19 USBD_INTRx USB Endpoint x Interrupt registers 14 27 USBD_MASKx USB Endpoint x Mask registers 14 30 USBD_MERR interrupt 14 43 USBD Module Configuration and Control register USBD_CTRL 14 21 US...

Page 1021: ...t Data Address Control register WPDACTL 20 13 Watchpoint Data Address Count Value registers WPDACNTx 20 11 Watchpoint Data Address registers WPDAx 20 11 Watchpoint Instruction Address Control register...

Page 1022: ...CTL Watchpoint Instruction Address Control register 20 7 WPIAx Watchpoint Instruction Address registers 20 5 WPSTAT Watchpoint Status register 20 14 wrap around buffer 5 7 wrapping bursts 13 9 write a...

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