ADSP-BF535 Blackfin Processor Hardware Reference
17-3
Real-Time Clock (RTC)
Writes to all RTC MMRs, except the RTC Interrupt Status register
(
RTC_ISTAT
), are synchronized to the RTC clock. If the prescaler is
enabled, writes are synchronized at a 1 Hz rate. If the prescaler is disabled,
writes are synchronized to the 32.768 kHz crystal rate. The Write Pending
Status bit in
RTC_ISTAT
indicates the progress of the write. The Write
Pending Status bit is set when a write occurs and is cleared when the write
is complete. The falling edge of the Write Pending Status bit causes the
Write Complete flag in
RTC_ISTAT
to be set. This flag can be configured in
RTC_ICTL
to cause an interrupt. Software does not have to wait for writes
to one RTC MMR to complete before writing to another RTC MMR.
There is no latency when reading RTC MMRs. The Write Pending Status
bit is set if any writes are in progress, and the Write Complete flag is set
only when all writes are complete.
Do not attempt another write to the same register without waiting
for the previous write to complete. Subsequent writes to the same
register are ignored if the previous write is not complete.
Do not read a register that has been written to until the Write
Complete flag is set. Always check the Write Pending Status bit
before attempting a read or write.
Writes to the RTC MMRs are synchronized to the RTC clock. When set-
ting the time of day with the prescaler enabled, do not factor in the delay
when writing to the RTC MMRs. The most accurate method of setting
the Real-Time Clock when the prescaler is enabled is to monitor the Sec-
onds (1 Hz) Event flag or to program an interrupt for this event and then
write the current time plus two seconds to the RTC Status register
(
RTC_STAT
) in the interrupt service routine (ISR).
The Seconds (1 Hz) Event flag is set on every positive edge of the RTC
clock. Because of this, the write to
RTC_STAT
occurs almost immediately
following the positive edge of the RTC clock. Since the value is registered
into the actual
RTC_STAT
register on the second clock edge after the write
occurs, adding two seconds to the real time before writing accounts for the
synchronization delay.
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...