Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 731 / 1022

ADSP-BF535 Blackfin Processor Hardware Reference 18-7
External Bus Interface Unit
EBIU Programming Model
This section describes the programming model of the EBIU. This model is
based on system memory-mapped registers (MMRs) used to program the
EBIU.
SCAS
O SDRAM Column Address Strobe pin
Connect to SDRAM’s
CAS
pin.
SWE
O SDRAM Write Enable pin
Connect to SDRAM’s
WE
pin.
SDQM[3]/ADDR[1]
SDQM[2:0]
O SDRAM Data Mask pins
Connect to SDRAM’s
DQM
pins. For 16-bit wide SDRAM
configurations
ADDR[1]
is output on
SDQM[3]
and
should be connected to SDRAM
A[0]
pin.
SMS[3:0]
O Memory select pin of external memory bank configured
for SDRAM
Connect to SDRAM’s
CS
(chip select) pin.
SA10
O SDRAM
A10
pin
SDRAM interface uses this pin to make refreshes possible
while the AMC is using the bus. Connect to SDRAM’s
A[10]
pin.
SCKE
O SDRAM Clock Enable pin
Connect to SDRAM’s
CKE
pin.
SCLK[0]
O SDRAM Clock output pin 0
Switches at system clock frequency. Connect to the
SDRAM’s
CLK
pin.
SCLK[1]
O SDRAM Clock output pin 1
Same frequency and timing as
SCLK[0]
. Provided to
reduce capacitive loading on
SCLK[0]
. Connect to the
SDRAM’s
CLK
pin.
Table 18-3. SDRAM Interface Signals (Cont’d)
EBIU Port Pins Pin Type Description