Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 5-13
Data Address Generators
The syntax is similar to post-modify addressing (index += modifier). For
Index registers, an M-register is used as the modifier. For Pointer registers,
another P-register is used as the modifier.
Consider the example,
I1 += M2
;
This instruction adds
M2
to
I1
and updates
I1
with the new value.
Memory Address Alignment
The ADSP-BF535 processor requires proper memory alignment to be
maintained for the data size being accessed. Unless exceptions are dis-
abled, violations of memory alignment cause an alignment exception.
Some instructions—for example, many of the Video ALU instructions—
automatically disable alignment exceptions because the data may not be
properly aligned when stored in memory. Alignment exceptions may be
disabled by issuing the
DISALGNEXPT
instruction in parallel with a
load/store operation.
Normally, the memory system requires two address alignments:
• 32-bit word load/stores are accessed on four-byte boundaries,
meaning the two least significant bits of the address are b#00.
• 16-bit word load/stores are accessed on two-byte boundaries,
meaning the least significant bit of the address must be b#0.