Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 310 / 1022

Working With Memory
6-84 ADSP-BF535 Blackfin Processor Hardware Reference
On the ADSP-BF535 processor, atomic operations use a test and set
instruction (
TESTSET
). The
TESTSET
instruction is a two-step process that
no other memory transaction can interrupt. The test portion of the
instruction is a load. The set portion sets the
CC
bit and stores a 1 to the
MSB at the same memory address. The set portion of the instruction is
conditional; that is, set occurs only if the value tested is 0.
The atomic operation can access the entire logical memory space except
the core MMR address region. However, atomicity may not be guaranteed
for all memory regions. The memory architecture treats atomic operations
as cache inhibited accesses even if the CPLB descriptor for the address
indicates a cache enabled access.
If a cache hit is detected, the line is flushed and invalidated before the
TESTSET
is allowed to proceed.

The ADSP-BF535 processor does not guarantee atomic access to
L1 memory space configured as SRAM. Consequently, semaphores
must not reside in L1 memory.
To ensure that all previous exceptions and interrupts have been processed
before the atomic operation begins, a
CSYNC
or
SSYNC
instruction may pre-
cede the
TESTSET
atomic access instruction.
Memory-Mapped Registers
The MMR reserved space is located at the top of the memory space
(0xFFC0 0000). This region is defined as non-cacheable and is divided
between the system MMRs (0xFFC0 0000-0xFFE0 0000) and core
MMRs (0xFFE0 0000-0xFFFF FFFF).

If strong ordering is required, place a synchronization instruction
after stores to MMRs. For more information, see
“Load/Store
Operation” on page 6-77 .