Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Memory Protection and Properties
6-56 ADSP-BF535 Blackfin Processor Hardware Reference
bank. If all four SDRAM banks are not fully populated with 128 MB of
SDRAM, the area from the end of bank 3 to address 0x2000 0000 is
reserved.
Each of the next four banks contains 64 MB and is dedicated to support
asynchronous memories.
The next region is reserved off-chip memory space. References to this
region do not generate external bus transactions. Writes have no effect on
external memory values, and reads return undefined values. The EBIU
generates an error response on the internal bus that generates a hardware
exception for a core access or, optionally, generates an interrupt from PCI
or a DMA channel, depending on where the access originated.
Because the PCI memory space is as large as the full memory address space
of the ADSP-BF535 processor, a segmented, or windowed, approach must
be employed, so that only a portion of one of the PCI address spaces is vis-
ible to the core at one time.
Memory Protection and Properties
This section describes the Memory Management Unit (MMU), memory
pages, CPLB management, MMU management, and CPLB registers.
Memory Management Unit
The Blackfin ADSP-BF535 processor contains a page based Memory
Management Unit (MMU). This mechanism provides control over cache-
ability of memory ranges, as well as management of protection attributes
at a page level. The MMU provides great flexibility in allocating memory
and I/O resources between tasks, with complete control over access rights
and cache behavior.