Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 13-3
PCI Bus Interface
The PCI specification refers to a 32-bit wide word as a double-word, and
to 16 bits as a word. This document defines 32 bits as a word, 16 bits as a
half word, and 8 bits as a byte.
PCI Device Function
The PCI device function supports a glueless logical and electrical interface
to a 3.3V PCI Revision 2.2-compliant bus platform (such as a PC) as a
single function device. This enables the development of intelligent PCI
peripheral systems based on the ADSP-BF535 processor. The
ADSP-BF535 processor PCI bus interface does not support multifunction
device applications; it supports one configuration space. The
ADSP-BF535 processor can also support a PCI/USB bridge function.
As a PCI device, the PCI controller can use the Memory DMA controller
to perform DMA transfers as required by the PCI host.
PCI Host Function
The ADSP-BF535 processor provides the PCI host (platform) functions
required to support and control numerous off-the-shelf PCI device func-
tions (ethernet controllers, bus bridges, and so on) in a system in which
the core processor is the host.
Processor Core Access to PCI Space
The Blackfin architecture defines only memory space; it does not define
I/O or configuration address spaces. The three memory spaces of PCI
space (memory, I/O, and configuration space) are mapped into the flat
32-bit core memory space. Since the PCI memory space is as large as the
full memory address space of the ADSP-BF535 processor, a segmented, or
windowed, approach must be employed, so that only portions of the PCI